Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/56592 )
Change subject: arch-arm: Replace mcrMrc15TrapToHyp with mcrMrc15Trap
......................................................................
arch-arm: Replace mcrMrc15TrapToHyp with mcrMrc15Trap
The mcrMrc15TrapToHyp helper is already called within mcrMrc15Trap
This achieves the following:
1) Simplifies ISA code
2) Aligns McrDc to Mcr instruction
Change-Id: I9b6bc621ad89230ad9dcf0563d8985d5757b4ae1
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56592
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/insts/misc.cc
M src/arch/arm/isa/insts/misc.isa
2 files changed, 30 insertions(+), 20 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 4bb02c9..8c46cb8 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2017-2018, 2021 Arm Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -362,14 +362,7 @@
Fault
McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData)
const
{
- bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
-
- if (hypTrap) {
- return std::make_shared<HypervisorTrap>(machInst, iss,
- EC_TRAPPED_CP15_MCR_MRC);
- } else {
- return NoFault;
- }
+ return mcrMrc15Trap(miscReg, machInst, xc->tcBase(), iss);
}
std::string
@@ -388,11 +381,9 @@
Fault
McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData)
const
{
- bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
-
- if (hypTrap) {
- return std::make_shared<HypervisorTrap>(machInst, iss,
- EC_TRAPPED_CP15_MCR_MRC);
+ Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), iss);
+ if (fault != NoFault) {
+ return fault;
} else {
return std::make_shared<UndefinedInstruction>(machInst, false,
mnemonic);
diff --git a/src/arch/arm/isa/insts/misc.isa
b/src/arch/arm/isa/insts/misc.isa
index 7253f85..c5ab3fa 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010-2013,2017-2020 ARM Limited
+// Copyright (c) 2010-2013,2017-2021 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -1115,7 +1115,7 @@
MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
RegId(MiscRegClass, preFlatDest)).index();
- bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm);
+ Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
@@ -1123,14 +1123,13 @@
// if we're in non secure PL1 mode then we can trap regardless
// of whether the register is accessible, in other modes we
// trap if only if the register IS accessible.
- if (undefined || (!can_write & !(hypTrap & !inUserMode(Cpsr) &
+ if (undefined || (!can_write && !(fault != NoFault
&& !inUserMode(Cpsr) &&
!isSecure(xc->tcBase())))) {
return std::make_shared<UndefinedInstruction>(machInst, false,
mnemonic);
}
- if (hypTrap) {
- return std::make_shared<HypervisorTrap>(machInst, imm,
-
EC_TRAPPED_CP15_MCR_MRC);
+ if (fault != NoFault) {
+ return fault;
}
'''
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9b6bc621ad89230ad9dcf0563d8985d5757b4ae1
Gerrit-Change-Number: 56592
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Richard Cooper <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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