Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55603 )
Change subject: arch-arm: Define MiscRegNum64 data structure
......................................................................
arch-arm: Define MiscRegNum64 data structure
Signed-off-by: Giacomo Travaglini <[email protected]>
Change-Id: Ia635bc068751edd9305a6e493e38e1a49aa64c4d
---
M src/arch/arm/regs/misc.hh
1 file changed, 61 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index 1a2f137..ffa131d 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1153,6 +1153,44 @@
extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
+ struct MiscRegNum64
+ {
+ MiscRegNum64(unsigned _op0, unsigned _op1,
+ unsigned _crn, unsigned _crm,
+ unsigned _op2)
+ : op0(_op0), op1(_op1), crn(_crn),
+ crm(_crm), op2(_op2)
+ {}
+
+ MiscRegNum64(const MiscRegNum64& rhs) = default;
+
+ bool
+ operator==(const MiscRegNum64 &other) const
+ {
+ return op0 == other.op0 &&
+ op1 == other.op1 &&
+ crn == other.crn &&
+ crm == other.crm &&
+ op2 == other.op2;
+ }
+
+ uint32_t
+ packed() const
+ {
+ return op0 << 14 |
+ op1 << 11 |
+ crn << 7 |
+ crm << 3 |
+ op2;
+ }
+
+ unsigned op0;
+ unsigned op1;
+ unsigned crn;
+ unsigned crm;
+ unsigned op2;
+ };
+
// Decodes 32-bit CP14 registers accessible through MCR/MRC
instructions
MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
unsigned crm, unsigned opc2);
@@ -2286,4 +2324,17 @@
} // namespace ArmISA
} // namespace gem5
+namespace std
+{
+template<>
+struct hash<gem5::ArmISA::MiscRegNum64>
+{
+ size_t
+ operator()(const gem5::ArmISA::MiscRegNum64& reg) const
+ {
+ return reg.packed();
+ }
+};
+} // namespace std
+
#endif // __ARCH_ARM_REGS_MISC_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia635bc068751edd9305a6e493e38e1a49aa64c4d
Gerrit-Change-Number: 55603
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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