Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50251 )
Change subject: cpu,arch: Put the name of the RegClass into the RegClass.
......................................................................
cpu,arch: Put the name of the RegClass into the RegClass.
Move the name of the RegClass out of constants which belong to the
RegId, and instead store them in the RegClass instances.
Change-Id: I1ddd4bc8467d5e3f178db7a11c8f8052f43fd7ec
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/cc.hh
M src/arch/arm/regs/int.hh
M src/arch/arm/regs/misc.hh
M src/arch/arm/regs/vec.hh
M src/arch/mips/isa.cc
M src/arch/mips/regs/float.hh
M src/arch/mips/regs/int.hh
M src/arch/mips/regs/misc.hh
M src/arch/power/isa.cc
M src/arch/power/regs/float.hh
M src/arch/power/regs/int.hh
M src/arch/power/regs/misc.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/regs/float.hh
M src/arch/riscv/regs/int.hh
M src/arch/riscv/regs/misc.hh
M src/arch/sparc/isa.cc
M src/arch/sparc/regs/float.hh
M src/arch/sparc/regs/int.hh
M src/arch/sparc/regs/misc.hh
M src/arch/x86/isa.cc
M src/arch/x86/regs/ccr.hh
M src/arch/x86/regs/float.hh
M src/arch/x86/regs/int.hh
M src/arch/x86/regs/misc.hh
M src/cpu/reg_class.cc
M src/cpu/reg_class.hh
28 files changed, 69 insertions(+), 70 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 82789fc..2635495 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -70,7 +70,7 @@
{
/* Not applicable to ARM */
-RegClass floatRegClass(FloatRegClass, 0, debug::FloatRegs);
+RegClass floatRegClass(FloatRegClass, "floating_point", 0,
debug::FloatRegs);
} // anonymous namespace
diff --git a/src/arch/arm/regs/cc.hh b/src/arch/arm/regs/cc.hh
index e3792cb..126d37d 100644
--- a/src/arch/arm/regs/cc.hh
+++ b/src/arch/arm/regs/cc.hh
@@ -63,8 +63,8 @@
} // namespace cc_reg
-inline constexpr RegClass ccRegClass(CCRegClass, cc_reg::NumRegs,
- debug::CCRegs);
+inline constexpr RegClass ccRegClass(CCRegClass, "condition_code",
+ cc_reg::NumRegs, debug::CCRegs);
namespace cc_reg
{
diff --git a/src/arch/arm/regs/int.hh b/src/arch/arm/regs/int.hh
index 9ff2498..8c8d591 100644
--- a/src/arch/arm/regs/int.hh
+++ b/src/arch/arm/regs/int.hh
@@ -163,7 +163,7 @@
} // namespace int_reg
-inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
+inline constexpr RegClass intRegClass(IntRegClass, "integer",
int_reg::NumRegs,
debug::IntRegs);
namespace int_reg
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index 969e284..fde7bdf 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -2201,7 +2201,7 @@
static inline MiscRegClassOps miscRegClassOps;
inline constexpr RegClass miscRegClass =
- RegClass(MiscRegClass, NUM_MISCREGS, debug::MiscRegs).
+ RegClass(MiscRegClass, "miscellaneous", NUM_MISCREGS,
debug::MiscRegs).
ops(miscRegClassOps);
// This mask selects bits of the CPSR that actually go in the CondCodes
diff --git a/src/arch/arm/regs/vec.hh b/src/arch/arm/regs/vec.hh
index 45eac30..d324c0f 100644
--- a/src/arch/arm/regs/vec.hh
+++ b/src/arch/arm/regs/vec.hh
@@ -99,14 +99,16 @@
static inline TypedRegClassOps<ArmISA::VecPredRegContainer>
vecPredRegClassOps;
inline constexpr RegClass vecRegClass =
- RegClass(VecRegClass, NumVecRegs, debug::VecRegs).
+ RegClass(VecRegClass, "vector", NumVecRegs, debug::VecRegs).
ops(vecRegClassOps).
regType<VecRegContainer>();
inline constexpr RegClass vecElemClass =
- RegClass(VecElemClass, NumVecRegs * NumVecElemPerVecReg,
debug::VecRegs).
+ RegClass(VecElemClass, "vector_element", NumVecRegs *
NumVecElemPerVecReg,
+ debug::VecRegs).
ops(vecRegElemClassOps);
inline constexpr RegClass vecPredRegClass =
- RegClass(VecPredRegClass, NumVecPredRegs, debug::VecPredRegs).
+ RegClass(VecPredRegClass, "vector_predicate", NumVecPredRegs,
+ debug::VecPredRegs).
ops(vecPredRegClassOps).
regType<VecPredRegContainer>();
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 7a95e49..f19f904 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -98,10 +98,12 @@
{
/* Not applicable to MIPS. */
-constexpr RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
-constexpr RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
-constexpr RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
-constexpr RegClass ccRegClass(CCRegClass, 0, debug::IntRegs);
+constexpr RegClass vecRegClass(VecRegClass, "vector", 1, debug::IntRegs);
+constexpr RegClass vecElemClass(VecElemClass, "vector_element", 2,
+ debug::IntRegs);
+constexpr RegClass vecPredRegClass(VecPredRegClass, "vector_predicate", 1,
+ debug::IntRegs);
+constexpr RegClass ccRegClass(CCRegClass, "condition_code", 0,
debug::IntRegs);
} // anonymous namespace
diff --git a/src/arch/mips/regs/float.hh b/src/arch/mips/regs/float.hh
index a61e61b..a7a93fe 100644
--- a/src/arch/mips/regs/float.hh
+++ b/src/arch/mips/regs/float.hh
@@ -89,8 +89,8 @@
} // namespace float_reg
-inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
- debug::FloatRegs);
+inline constexpr RegClass floatRegClass(FloatRegClass, "floating_point",
+ float_reg::NumRegs, debug::FloatRegs);
namespace float_reg
{
diff --git a/src/arch/mips/regs/int.hh b/src/arch/mips/regs/int.hh
index 1981d0a..b8bee51 100644
--- a/src/arch/mips/regs/int.hh
+++ b/src/arch/mips/regs/int.hh
@@ -119,7 +119,7 @@
} // namespace int_reg
-inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
+inline constexpr RegClass intRegClass(IntRegClass, "integer",
int_reg::NumRegs,
debug::IntRegs);
namespace int_reg
diff --git a/src/arch/mips/regs/misc.hh b/src/arch/mips/regs/misc.hh
index 90251d6..84ed63e 100644
--- a/src/arch/mips/regs/misc.hh
+++ b/src/arch/mips/regs/misc.hh
@@ -200,8 +200,8 @@
} // namespace misc_reg
-inline constexpr RegClass miscRegClass(MiscRegClass, misc_reg::NumRegs,
- debug::MiscRegs);
+inline constexpr RegClass miscRegClass(MiscRegClass, "miscellaneous",
+ misc_reg::NumRegs, debug::MiscRegs);
} // namespace MipsISA
} // namespace gem5
diff --git a/src/arch/power/isa.cc b/src/arch/power/isa.cc
index 0646c11..541b347 100644
--- a/src/arch/power/isa.cc
+++ b/src/arch/power/isa.cc
@@ -52,10 +52,11 @@
namespace
{
-RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
-RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
-RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
-RegClass ccRegClass(CCRegClass, 0, debug::IntRegs);
+RegClass vecRegClass(VecRegClass, "vector", 1, debug::IntRegs);
+RegClass vecElemClass(VecElemClass, "vector_element", 2, debug::IntRegs);
+RegClass vecPredRegClass(VecPredRegClass, "vector_predicate", 1,
+ debug::IntRegs);
+RegClass ccRegClass(CCRegClass, "condition_code", 0, debug::IntRegs);
} // anonymous namespace
diff --git a/src/arch/power/regs/float.hh b/src/arch/power/regs/float.hh
index 11f1aab..94d575d 100644
--- a/src/arch/power/regs/float.hh
+++ b/src/arch/power/regs/float.hh
@@ -46,8 +46,8 @@
} // namespace float_reg
-inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
- debug::FloatRegs);
+inline constexpr RegClass floatRegClass(FloatRegClass, "floating_point",
+ float_reg::NumRegs, debug::FloatRegs);
} // namespace PowerISA
} // namespace gem5
diff --git a/src/arch/power/regs/int.hh b/src/arch/power/regs/int.hh
index cdd2d6e..3728cb2 100644
--- a/src/arch/power/regs/int.hh
+++ b/src/arch/power/regs/int.hh
@@ -95,7 +95,7 @@
} // namespace int_reg
-inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
+inline constexpr RegClass intRegClass(IntRegClass, "integer",
int_reg::NumRegs,
debug::IntRegs);
namespace int_reg
diff --git a/src/arch/power/regs/misc.hh b/src/arch/power/regs/misc.hh
index 1ab8e42..885da3a 100644
--- a/src/arch/power/regs/misc.hh
+++ b/src/arch/power/regs/misc.hh
@@ -48,8 +48,8 @@
const char * const miscRegName[NUM_MISCREGS] = {
};
-inline constexpr RegClass miscRegClass(MiscRegClass, NUM_MISCREGS,
- debug::MiscRegs);
+inline constexpr RegClass miscRegClass(MiscRegClass, "miscellaneous",
+ NUM_MISCREGS, debug::MiscRegs);
BitUnion32(Cr)
SubBitUnion(cr0, 31, 28)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index caf8b96..edc81f8 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -186,10 +186,11 @@
{
/* Not applicable to RISCV */
-RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
-RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
-RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
-RegClass ccRegClass(CCRegClass, 0, debug::IntRegs);
+RegClass vecRegClass(VecRegClass, "vector", 1, debug::IntRegs);
+RegClass vecElemClass(VecElemClass, "vector_element", 2, debug::IntRegs);
+RegClass vecPredRegClass(VecPredRegClass, "vector_predicate", 1,
+ debug::IntRegs);
+RegClass ccRegClass(CCRegClass, "condition_code", 0, debug::IntRegs);
} // anonymous namespace
diff --git a/src/arch/riscv/regs/float.hh b/src/arch/riscv/regs/float.hh
index 5797a49..757c28f 100644
--- a/src/arch/riscv/regs/float.hh
+++ b/src/arch/riscv/regs/float.hh
@@ -139,8 +139,8 @@
} // namespace float_reg
-inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
- debug::FloatRegs);
+inline constexpr RegClass floatRegClass(FloatRegClass, "floating_point",
+ float_reg::NumRegs, debug::FloatRegs);
namespace float_reg
{
diff --git a/src/arch/riscv/regs/int.hh b/src/arch/riscv/regs/int.hh
index 3ca73ac..139ce16 100644
--- a/src/arch/riscv/regs/int.hh
+++ b/src/arch/riscv/regs/int.hh
@@ -81,7 +81,7 @@
} // namespace int_reg
-inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
+inline constexpr RegClass intRegClass(IntRegClass, "integer",
int_reg::NumRegs,
debug::IntRegs);
namespace int_reg
diff --git a/src/arch/riscv/regs/misc.hh b/src/arch/riscv/regs/misc.hh
index 8337d61..61f8613 100644
--- a/src/arch/riscv/regs/misc.hh
+++ b/src/arch/riscv/regs/misc.hh
@@ -192,8 +192,8 @@
NUM_MISCREGS
};
-inline constexpr RegClass miscRegClass(MiscRegClass, NUM_MISCREGS,
- debug::MiscRegs);
+inline constexpr RegClass miscRegClass(MiscRegClass, "miscellaneous",
+ NUM_MISCREGS, debug::MiscRegs);
enum CSRIndex
{
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index f493079..f940424 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -69,10 +69,11 @@
{
/* Not applicable for SPARC */
-RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
-RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
-RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
-RegClass ccRegClass(CCRegClass, 0, debug::IntRegs);
+RegClass vecRegClass(VecRegClass, "vector", 1, debug::IntRegs);
+RegClass vecElemClass(VecElemClass, "vector_element", 2, debug::IntRegs);
+RegClass vecPredRegClass(VecPredRegClass, "vector_predicate", 1,
+ debug::IntRegs);
+RegClass ccRegClass(CCRegClass, "condition_code", 0, debug::IntRegs);
} // anonymous namespace
diff --git a/src/arch/sparc/regs/float.hh b/src/arch/sparc/regs/float.hh
index 8398b73..a95eb78 100644
--- a/src/arch/sparc/regs/float.hh
+++ b/src/arch/sparc/regs/float.hh
@@ -46,8 +46,8 @@
} // namespace float_reg
-inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
- debug::FloatRegs);
+inline constexpr RegClass floatRegClass(FloatRegClass, "floating_point",
+ float_reg::NumRegs, debug::FloatRegs);
} // namespace SparcISA
} // namespace gem5
diff --git a/src/arch/sparc/regs/int.hh b/src/arch/sparc/regs/int.hh
index b1bfcae..9cc2b2e 100644
--- a/src/arch/sparc/regs/int.hh
+++ b/src/arch/sparc/regs/int.hh
@@ -68,7 +68,7 @@
} // namespace int_reg
-inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
+inline constexpr RegClass intRegClass(IntRegClass, "integer",
int_reg::NumRegs,
debug::IntRegs);
namespace int_reg
diff --git a/src/arch/sparc/regs/misc.hh b/src/arch/sparc/regs/misc.hh
index 0f008c3..2002bf3 100644
--- a/src/arch/sparc/regs/misc.hh
+++ b/src/arch/sparc/regs/misc.hh
@@ -174,8 +174,8 @@
const int NumMiscRegs = MISCREG_NUMMISCREGS;
-inline constexpr RegClass miscRegClass(MiscRegClass, NumMiscRegs,
- debug::MiscRegs);
+inline constexpr RegClass miscRegClass(MiscRegClass, "miscellaneous",
+ NumMiscRegs, debug::MiscRegs);
} // namespace SparcISA
} // namespace gem5
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 8567956..18e0ddf6 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -142,9 +142,10 @@
{
/* Not applicable to X86 */
-RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
-RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
-RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
+RegClass vecRegClass(VecRegClass, "vector", 1, debug::IntRegs);
+RegClass vecElemClass(VecElemClass, "vector_element", 2, debug::IntRegs);
+RegClass vecPredRegClass(VecPredRegClass, "vector_predicate", 1,
+ debug::IntRegs);
} // anonymous namespace
diff --git a/src/arch/x86/regs/ccr.hh b/src/arch/x86/regs/ccr.hh
index 80c7392..c05ff52 100644
--- a/src/arch/x86/regs/ccr.hh
+++ b/src/arch/x86/regs/ccr.hh
@@ -61,8 +61,8 @@
} // namesapce cc_reg
-inline constexpr RegClass ccRegClass(CCRegClass, cc_reg::NumRegs,
- debug::CCRegs);
+inline constexpr RegClass ccRegClass(CCRegClass, "condition_code",
+ cc_reg::NumRegs, debug::CCRegs);
namespace cc_reg
{
diff --git a/src/arch/x86/regs/float.hh b/src/arch/x86/regs/float.hh
index e5150a9..30c3e17 100644
--- a/src/arch/x86/regs/float.hh
+++ b/src/arch/x86/regs/float.hh
@@ -121,8 +121,8 @@
} // namespace float_reg
-inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
- debug::FloatRegs);
+inline constexpr RegClass floatRegClass(FloatRegClass, "floating_point",
+ float_reg::NumRegs, debug::FloatRegs);
namespace float_reg
{
diff --git a/src/arch/x86/regs/int.hh b/src/arch/x86/regs/int.hh
index 9b7b814..56ac923 100644
--- a/src/arch/x86/regs/int.hh
+++ b/src/arch/x86/regs/int.hh
@@ -102,7 +102,7 @@
} // namespace int_reg
-inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
+inline constexpr RegClass intRegClass(IntRegClass, "integer",
int_reg::NumRegs,
debug::IntRegs);
namespace int_reg
diff --git a/src/arch/x86/regs/misc.hh b/src/arch/x86/regs/misc.hh
index aa854e9..4893082 100644
--- a/src/arch/x86/regs/misc.hh
+++ b/src/arch/x86/regs/misc.hh
@@ -538,8 +538,8 @@
} // namespace misc_reg
-inline constexpr RegClass miscRegClass(MiscRegClass, misc_reg::NumRegs,
- debug::MiscRegs);
+inline constexpr RegClass miscRegClass(MiscRegClass, "miscellaneous",
+ misc_reg::NumRegs, debug::MiscRegs);
/**
* A type to describe the condition code bits of the RFLAGS register,
diff --git a/src/cpu/reg_class.cc b/src/cpu/reg_class.cc
index af8010b..df728aa 100644
--- a/src/cpu/reg_class.cc
+++ b/src/cpu/reg_class.cc
@@ -96,14 +96,4 @@
return out.str();
}
-const char *RegId::regClassStrings[] = {
- "IntRegClass",
- "FloatRegClass",
- "VecRegClass",
- "VecElemClass",
- "VecPredRegClass",
- "CCRegClass",
- "MiscRegClass"
-};
-
} // namespace gem5
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index cfc86ee..eaf1769 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -86,6 +86,7 @@
{
private:
RegClassType _type;
+ const char *_name;
size_t _size;
size_t _regBytes = sizeof(RegVal);
@@ -99,9 +100,9 @@
const debug::Flag &debugFlag;
public:
- constexpr RegClass(RegClassType type, size_t new_size,
- const debug::Flag &debug_flag) :
- _type(type), _size(new_size), debugFlag(debug_flag)
+ constexpr RegClass(RegClassType type, const char *new_name,
+ size_t new_size, const debug::Flag &debug_flag) :
+ _type(type), _name(new_name), _size(new_size),
debugFlag(debug_flag)
{}
constexpr RegClass
@@ -123,6 +124,7 @@
}
constexpr RegClassType type() const { return _type; }
+ constexpr const char *name() const { return _name; }
constexpr size_t size() const { return _size; }
constexpr size_t regBytes() const { return _regBytes; }
constexpr size_t regShift() const { return _regShift; }
@@ -144,7 +146,7 @@
};
inline constexpr RegClass
- invalidRegClass(InvalidRegClass, 0, debug::InvalidReg);
+ invalidRegClass(InvalidRegClass, "invalid", 0, debug::InvalidReg);
/** Register ID: describe an architectural register with its class and
index.
* This structure is used instead of just the register index to
disambiguate
@@ -154,7 +156,6 @@
class RegId
{
protected:
- static const char* regClassStrings[];
const RegClass *_regClass = nullptr;
RegIndex regIdx;
int numPinnedWrites;
@@ -223,7 +224,7 @@
constexpr const char*
className() const
{
- return regClassStrings[classValue()];
+ return _regClass->name();
}
int getNumPinnedWrites() const { return numPinnedWrites; }
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50251
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1ddd4bc8467d5e3f178db7a11c8f8052f43fd7ec
Gerrit-Change-Number: 50251
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
