Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48150 )
Change subject: arch-arm: Add a shared L2 TLB to the default ArmMMU
......................................................................
arch-arm: Add a shared L2 TLB to the default ArmMMU
JIRA: https://gem5.atlassian.net/browse/GEM5-790
Change-Id: I542c287a99c8b277afb4cd939c09521798dcf2f8
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/arch/arm/ArmMMU.py
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/src/arch/arm/ArmMMU.py b/src/arch/arm/ArmMMU.py
index 0112bc9..6b5aaaa 100644
--- a/src/arch/arm/ArmMMU.py
+++ b/src/arch/arm/ArmMMU.py
@@ -64,13 +64,17 @@
cxx_class = 'gem5::ArmISA::MMU'
cxx_header = 'arch/arm/mmu.hh'
- itb = ArmTLB(entry_type="instruction")
- dtb = ArmTLB(entry_type="data")
-
cxx_exports = [
PyBindMethod('wireComponents'),
]
+ # L1 TLBs
+ itb = ArmTLB(entry_type="instruction")
+ dtb = ArmTLB(entry_type="data")
+
+ # L2 TLBs
+ l2_shared = ArmTLB(entry_type="unified", size=1280)
+
stage2_itb = Param.ArmTLB(
ArmStage2TLB(entry_type="instruction"),
"Stage 2 Instruction TLB")
@@ -91,6 +95,9 @@
sys = Param.System(Parent.any, "system object parameter")
def init(self):
+ self.itb.setNextLevel(self.l2_shared.getCCObject())
+ self.dtb.setNextLevel(self.l2_shared.getCCObject())
+
self.getCCObject().wireComponents()
super(ArmMMU, self).init()
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I542c287a99c8b277afb4cd939c09521798dcf2f8
Gerrit-Change-Number: 48150
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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