Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/37955 )
Change subject: arch-arm: Make TLB misses from a sw prefetch visible
......................................................................
arch-arm: Make TLB misses from a sw prefetch visible
While a TLB hit caused by a prefetching operation is visible in terms
of TLB stats update, this is not the case for a TLB miss, which is
invisible to the stats as it is now.
This patch is realigning the behaviour to be more consistent: we will
always update the stats regardless of whether the access caused a
TLB hit/miss
Change-Id: I161e04fc09a0dbba7468a52848aa7710d1476e19
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37955
Reviewed-by: Tiago Mück <[email protected]>
Reviewed-by: Richard Cooper <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/tlb.cc
1 file changed, 8 insertions(+), 7 deletions(-)
Approvals:
Tiago Mück: Looks good to me, approved
Richard Cooper: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 8e5b3ca..b1c4dff 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1583,6 +1583,14 @@
*te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false,
target_el,
false);
if (*te == NULL) {
+ // Note, we are updating the stats for sw prefetching misses as
well
+ if (is_fetch)
+ stats.instMisses++;
+ else if (is_write)
+ stats.writeMisses++;
+ else
+ stats.readMisses++;
+
if (req->isPrefetch()) {
// if the request is a prefetch don't attempt to fill the TLB
or go
// any further with the memory access (here we can safely use
the
@@ -1592,13 +1600,6 @@
vaddr_tainted, ArmFault::PrefetchTLBMiss, isStage2);
}
- if (is_fetch)
- stats.instMisses++;
- else if (is_write)
- stats.writeMisses++;
- else
- stats.readMisses++;
-
// start translation table walk, pass variables rather than
// re-retreaving in table walker for speed
DPRINTF(TLB, "TLB Miss: Starting hardware table walker
for %#x(%d:%d)\n",
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37955
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I161e04fc09a0dbba7468a52848aa7710d1476e19
Gerrit-Change-Number: 37955
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Ciro Santilli <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-Reviewer: Richard Cooper <[email protected]>
Gerrit-Reviewer: Tiago Mück <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
