Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/43727 )
Change subject: cpu: Improve MemTest
......................................................................
cpu: Improve MemTest
To make it easy to select memory sizes, make the base addresses
explicit parameters.
Change-Id: I337a10b539bf734c6f99f99eaa2daa252be5a9d2
Signed-off-by: Alexander Klimov <[email protected]>
---
M src/cpu/testers/memtest/MemTest.py
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/memtest/memtest.hh
3 files changed, 16 insertions(+), 13 deletions(-)
diff --git a/src/cpu/testers/memtest/MemTest.py
b/src/cpu/testers/memtest/MemTest.py
index eebcd97..a91c946 100644
--- a/src/cpu/testers/memtest/MemTest.py
+++ b/src/cpu/testers/memtest/MemTest.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2015 ARM Limited
+# Copyright (c) 2015, 2021 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -49,6 +49,10 @@
# touched, and an optional stop condition
interval = Param.Cycles(1, "Interval between request packets")
size = Param.Unsigned(65536, "Size of memory region to use (bytes)")
+ base_addr_1 = Param.Addr(0x100000, "Start of the first testing region")
+ base_addr_2 = Param.Addr(0x400000, "Start of the second testing
region")
+ uncacheable_base_addr = Param.Addr(
+ 0x800000, "Start of the uncacheable testing region")
max_loads = Param.Counter(0, "Number of loads to execute before
exiting")
# Control the mix of packets and if functional accesses are part of
diff --git a/src/cpu/testers/memtest/memtest.cc
b/src/cpu/testers/memtest/memtest.cc
index c2d2bad..88cc680 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, 2019 ARM Limited
+ * Copyright (c) 2015, 2019, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -48,7 +48,7 @@
#include "sim/stats.hh"
#include "sim/system.hh"
-unsigned int TESTER_ALLOCATOR = 0;
+static unsigned int TESTER_ALLOCATOR = 0;
bool
MemTest::CpuPort::recvTimingResp(PacketPtr pkt)
@@ -92,6 +92,9 @@
requestorId(p.system->getRequestorId(this)),
blockSize(p.system->cacheLineSize()),
blockAddrMask(blockSize - 1),
+ baseAddr1(p.base_addr_1),
+ baseAddr2(p.base_addr_2),
+ uncacheAddr(p.uncacheable_base_addr),
progressInterval(p.progress_interval),
progressCheck(p.progress_check),
nextProgressMessage(p.progress_interval),
@@ -103,10 +106,6 @@
fatal_if(id >= blockSize, "Too many testers, only %d allowed\n",
blockSize - 1);
- baseAddr1 = 0x100000;
- baseAddr2 = 0x400000;
- uncacheAddr = 0x800000;
-
// set up counters
numReads = 0;
numWrites = 0;
diff --git a/src/cpu/testers/memtest/memtest.hh
b/src/cpu/testers/memtest/memtest.hh
index d806d7a..ec9443b 100644
--- a/src/cpu/testers/memtest/memtest.hh
+++ b/src/cpu/testers/memtest/memtest.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -41,8 +41,8 @@
#ifndef __CPU_MEMTEST_MEMTEST_HH__
#define __CPU_MEMTEST_MEMTEST_HH__
-#include <set>
#include <unordered_map>
+#include <unordered_set>
#include "base/statistics.hh"
#include "mem/port.hh"
@@ -130,7 +130,7 @@
unsigned int id;
- std::set<Addr> outstandingAddrs;
+ std::unordered_set<Addr> outstandingAddrs;
// store the expected value for the addresses we have touched
std::unordered_map<Addr, uint8_t> referenceData;
@@ -150,9 +150,9 @@
return (addr & ~blockAddrMask);
}
- Addr baseAddr1;
- Addr baseAddr2;
- Addr uncacheAddr;
+ const Addr baseAddr1;
+ const Addr baseAddr2;
+ const Addr uncacheAddr;
const unsigned progressInterval; // frequency of progress reports
const Cycles progressCheck;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I337a10b539bf734c6f99f99eaa2daa252be5a9d2
Gerrit-Change-Number: 43727
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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