Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41899 )
Change subject: cpu: Eliminate the unused "lane" interface from the
ThreadContext.
......................................................................
cpu: Eliminate the unused "lane" interface from the ThreadContext.
If someone needs to access a component of a vector register, they can do
so through the other interfaces.
Change-Id: Idf1d9b68339eb31b95d4a347548240aa9d2a85cc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41899
Reviewed-by: Gabe Black <[email protected]>
Maintainer: Gabe Black <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/fastmodel/iris/thread_context.hh
M src/cpu/checker/thread_context.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/regfile.hh
M src/cpu/o3/thread_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
7 files changed, 0 insertions(+), 393 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh
b/src/arch/arm/fastmodel/iris/thread_context.hh
index b7ea0b5..019baca 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -283,62 +283,6 @@
panic("%s not implemented.", __FUNCTION__);
}
- /** Vector Register Lane Interfaces. */
- /** @{ */
- /** Reads source vector 8bit operand. */
- ConstVecLane8
- readVec8BitLaneReg(const RegId ®) const override
- {
- panic("%s not implemented.", __FUNCTION__);
- }
-
- /** Reads source vector 16bit operand. */
- ConstVecLane16
- readVec16BitLaneReg(const RegId ®) const override
- {
- panic("%s not implemented.", __FUNCTION__);
- }
-
- /** Reads source vector 32bit operand. */
- ConstVecLane32
- readVec32BitLaneReg(const RegId ®) const override
- {
- panic("%s not implemented.", __FUNCTION__);
- }
-
- /** Reads source vector 64bit operand. */
- ConstVecLane64
- readVec64BitLaneReg(const RegId ®) const override
- {
- panic("%s not implemented.", __FUNCTION__);
- }
-
- /** Write a lane of the destination vector register. */
- void
- setVecLane(const RegId ®, const LaneData<LaneSize::Byte> &val)
override
- {
- panic("%s not implemented.", __FUNCTION__);
- }
- void
- setVecLane(const RegId ®,
- const LaneData<LaneSize::TwoByte> &val) override
- {
- panic("%s not implemented.", __FUNCTION__);
- }
- void
- setVecLane(const RegId ®,
- const LaneData<LaneSize::FourByte> &val) override
- {
- panic("%s not implemented.", __FUNCTION__);
- }
- void
- setVecLane(const RegId ®,
- const LaneData<LaneSize::EightByte> &val) override
- {
- panic("%s not implemented.", __FUNCTION__);
- }
- /** @} */
-
const VecElem &
readVecElem(const RegId ®) const override
{
diff --git a/src/cpu/checker/thread_context.hh
b/src/cpu/checker/thread_context.hh
index 338e871..661c710 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -249,63 +249,6 @@
return actualTC->getWritableVecReg(reg);
}
- /** Vector Register Lane Interfaces. */
- /** @{ */
- /** Reads source vector 8bit operand. */
- ConstVecLane8
- readVec8BitLaneReg(const RegId ®) const override
- {
- return actualTC->readVec8BitLaneReg(reg);
- }
-
- /** Reads source vector 16bit operand. */
- ConstVecLane16
- readVec16BitLaneReg(const RegId ®) const override
- {
- return actualTC->readVec16BitLaneReg(reg);
- }
-
- /** Reads source vector 32bit operand. */
- ConstVecLane32
- readVec32BitLaneReg(const RegId ®) const override
- {
- return actualTC->readVec32BitLaneReg(reg);
- }
-
- /** Reads source vector 64bit operand. */
- ConstVecLane64
- readVec64BitLaneReg(const RegId ®) const override
- {
- return actualTC->readVec64BitLaneReg(reg);
- }
-
- /** Write a lane of the destination vector register. */
- virtual void
- setVecLane(const RegId ®,
- const LaneData<LaneSize::Byte> &val) override
- {
- return actualTC->setVecLane(reg, val);
- }
- virtual void
- setVecLane(const RegId ®,
- const LaneData<LaneSize::TwoByte> &val) override
- {
- return actualTC->setVecLane(reg, val);
- }
- virtual void
- setVecLane(const RegId ®,
- const LaneData<LaneSize::FourByte> &val) override
- {
- return actualTC->setVecLane(reg, val);
- }
- virtual void
- setVecLane(const RegId ®,
- const LaneData<LaneSize::EightByte> &val) override
- {
- return actualTC->setVecLane(reg, val);
- }
- /** @} */
-
const TheISA::VecElem &
readVecElem(const RegId& reg) const override
{
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 596fa19..73b86af 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -345,37 +345,6 @@
void vecRenameMode(Enums::VecRegRenameMode vec_mode)
{ vecMode = vec_mode; }
- /**
- * Read physical vector register lane
- */
- template<typename VE, int LaneIdx>
- VecLaneT<VE, true>
- readVecLane(PhysRegIdPtr phys_reg) const
- {
- cpuStats.vecRegfileReads++;
- return regFile.readVecLane<VE, LaneIdx>(phys_reg);
- }
-
- /**
- * Read physical vector register lane
- */
- template<typename VE>
- VecLaneT<VE, true>
- readVecLane(PhysRegIdPtr phys_reg) const
- {
- cpuStats.vecRegfileReads++;
- return regFile.readVecLane<VE>(phys_reg);
- }
-
- /** Write a lane of the destination vector register. */
- template<typename LD>
- void
- setVecLane(PhysRegIdPtr phys_reg, const LD& val)
- {
- cpuStats.vecRegfileWrites++;
- return regFile.setVecLane(phys_reg, val);
- }
-
const TheISA::VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
const TheISA::VecPredRegContainer&
@@ -407,27 +376,6 @@
/** Read architectural vector register for modification. */
TheISA::VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID
tid);
- /** Read architectural vector register lane. */
- template<typename VE>
- VecLaneT<VE, true>
- readArchVecLane(int reg_idx, int lId, ThreadID tid) const
- {
- PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
- RegId(VecRegClass, reg_idx));
- return readVecLane<VE>(phys_reg);
- }
-
-
- /** Write a lane of the destination vector register. */
- template<typename LD>
- void
- setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val)
- {
- PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
- RegId(VecRegClass, reg_idx));
- setVecLane(phys_reg, val);
- }
-
const TheISA::VecElem& readArchVecElem(const RegIndex& reg_idx,
const ElemIndex& ldx, ThreadID tid) const;
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index ec8716b..71f2e72 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -216,36 +216,6 @@
return const_cast<TheISA::VecRegContainer&>(readVecReg(phys_reg));
}
- /** Reads a vector register lane. */
- template <typename VE, int LaneIdx>
- VecLaneT<VE, true>
- readVecLane(PhysRegIdPtr phys_reg) const
- {
- return readVecReg(phys_reg).laneView<VE, LaneIdx>();
- }
-
- /** Reads a vector register lane. */
- template <typename VE>
- VecLaneT<VE, true>
- readVecLane(PhysRegIdPtr phys_reg) const
- {
- return readVecReg(phys_reg).laneView<VE>(phys_reg->elemIndex());
- }
-
- /** Get a vector register lane for modification. */
- template <typename LD>
- void
- setVecLane(PhysRegIdPtr phys_reg, const LD& val)
- {
- assert(phys_reg->isVectorPhysReg());
-
- DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n",
- int(phys_reg->index()), phys_reg->elemIndex(), val);
-
- vectorRegFile[phys_reg->index()].laneView<typename
LD::UnderlyingType>(
- phys_reg->elemIndex()) = val;
- }
-
/** Reads a vector element. */
const TheISA::VecElem &
readVecElem(PhysRegIdPtr phys_reg) const
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index f4d116c..8dd4165 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -219,67 +219,6 @@
return getWritableVecRegFlat(flattenRegId(id).index());
}
- /** Vector Register Lane Interfaces. */
- /** @{ */
- /** Reads source vector 8bit operand. */
- ConstVecLane8
- readVec8BitLaneReg(const RegId& id) const override
- {
- return readVecLaneFlat<uint8_t>(flattenRegId(id).index(),
- id.elemIndex());
- }
-
- /** Reads source vector 16bit operand. */
- ConstVecLane16
- readVec16BitLaneReg(const RegId& id) const override
- {
- return readVecLaneFlat<uint16_t>(flattenRegId(id).index(),
- id.elemIndex());
- }
-
- /** Reads source vector 32bit operand. */
- ConstVecLane32
- readVec32BitLaneReg(const RegId& id) const override
- {
- return readVecLaneFlat<uint32_t>(flattenRegId(id).index(),
- id.elemIndex());
- }
-
- /** Reads source vector 64bit operand. */
- ConstVecLane64
- readVec64BitLaneReg(const RegId& id) const override
- {
- return readVecLaneFlat<uint64_t>(flattenRegId(id).index(),
- id.elemIndex());
- }
-
- /** Write a lane of the destination vector register. */
- void
- setVecLane(const RegId& reg,
- const LaneData<LaneSize::Byte>& val) override
- {
- return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(),
val);
- }
- void
- setVecLane(const RegId& reg,
- const LaneData<LaneSize::TwoByte>& val) override
- {
- return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(),
val);
- }
- void
- setVecLane(const RegId& reg,
- const LaneData<LaneSize::FourByte>& val) override
- {
- return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(),
val);
- }
- void
- setVecLane(const RegId& reg,
- const LaneData<LaneSize::EightByte>& val) override
- {
- return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(),
val);
- }
- /** @} */
-
const TheISA::VecElem &
readVecElem(const RegId& reg) const override
{
@@ -443,21 +382,6 @@
void setVecRegFlat(RegIndex idx,
const TheISA::VecRegContainer& val) override;
- template <typename VE>
- VecLaneT<VE, true>
- readVecLaneFlat(RegIndex idx, int lId) const
- {
- return cpu->template readArchVecLane<VE>(idx, lId,
- thread->threadId());
- }
-
- template <typename LD>
- void
- setVecLaneFlat(int idx, int lId, const LD& val)
- {
- cpu->template setArchVecLane(idx, lId, thread->threadId(), val);
- }
-
const TheISA::VecElem &readVecElemFlat(RegIndex idx,
const ElemIndex& elemIndex) const override;
void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 317f947..b2321c4 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -310,85 +310,6 @@
return regVal;
}
- /** Vector Register Lane Interfaces. */
- /** @{ */
- /** Reads source vector <T> operand. */
- template <typename T>
- VecLaneT<T, true>
- readVecLane(const RegId& reg) const
- {
- int flatIndex = isa->flattenVecIndex(reg.index());
- assert(flatIndex < TheISA::NumVecRegs);
- auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex());
- DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n",
- reg.index(), flatIndex, reg.elemIndex(), regVal);
- return regVal;
- }
-
- /** Reads source vector 8bit operand. */
- virtual ConstVecLane8
- readVec8BitLaneReg(const RegId ®) const override
- {
- return readVecLane<uint8_t>(reg);
- }
-
- /** Reads source vector 16bit operand. */
- virtual ConstVecLane16
- readVec16BitLaneReg(const RegId ®) const override
- {
- return readVecLane<uint16_t>(reg);
- }
-
- /** Reads source vector 32bit operand. */
- virtual ConstVecLane32
- readVec32BitLaneReg(const RegId ®) const override
- {
- return readVecLane<uint32_t>(reg);
- }
-
- /** Reads source vector 64bit operand. */
- virtual ConstVecLane64
- readVec64BitLaneReg(const RegId ®) const override
- {
- return readVecLane<uint64_t>(reg);
- }
-
- /** Write a lane of the destination vector register. */
- template <typename LD>
- void
- setVecLaneT(const RegId ®, const LD &val)
- {
- int flatIndex = isa->flattenVecIndex(reg.index());
- assert(flatIndex < TheISA::NumVecRegs);
- setVecLaneFlat(flatIndex, reg.elemIndex(), val);
- DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n",
- reg.index(), flatIndex, reg.elemIndex(), val);
- }
- virtual void
- setVecLane(const RegId ®, const LaneData<LaneSize::Byte> &val)
override
- {
- return setVecLaneT(reg, val);
- }
- virtual void
- setVecLane(const RegId ®,
- const LaneData<LaneSize::TwoByte> &val) override
- {
- return setVecLaneT(reg, val);
- }
- virtual void
- setVecLane(const RegId ®,
- const LaneData<LaneSize::FourByte> &val) override
- {
- return setVecLaneT(reg, val);
- }
- virtual void
- setVecLane(const RegId ®,
- const LaneData<LaneSize::EightByte> &val) override
- {
- return setVecLaneT(reg, val);
- }
- /** @} */
-
const TheISA::VecElem &
readVecElem(const RegId ®) const override
{
@@ -609,20 +530,6 @@
vecRegs[reg] = val;
}
- template <typename T>
- VecLaneT<T, true>
- readVecLaneFlat(RegIndex reg, int lId) const
- {
- return vecRegs[reg].laneView<T>(lId);
- }
-
- template <typename LD>
- void
- setVecLaneFlat(RegIndex reg, int lId, const LD &val)
- {
- vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val;
- }
-
const TheISA::VecElem &
readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const
override
{
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 874146a..75f6f5a 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -205,35 +205,6 @@
readVecReg(const RegId& reg) const = 0;
virtual TheISA::VecRegContainer& getWritableVecReg(const RegId& reg) =
0;
- /** Vector Register Lane Interfaces. */
- /** @{ */
- /** Reads source vector 8bit operand. */
- virtual ConstVecLane8
- readVec8BitLaneReg(const RegId& reg) const = 0;
-
- /** Reads source vector 16bit operand. */
- virtual ConstVecLane16
- readVec16BitLaneReg(const RegId& reg) const = 0;
-
- /** Reads source vector 32bit operand. */
- virtual ConstVecLane32
- readVec32BitLaneReg(const RegId& reg) const = 0;
-
- /** Reads source vector 64bit operand. */
- virtual ConstVecLane64
- readVec64BitLaneReg(const RegId& reg) const = 0;
-
- /** Write a lane of the destination vector register. */
- virtual void setVecLane(const RegId& reg,
- const LaneData<LaneSize::Byte>& val) = 0;
- virtual void setVecLane(const RegId& reg,
- const LaneData<LaneSize::TwoByte>& val) = 0;
- virtual void setVecLane(const RegId& reg,
- const LaneData<LaneSize::FourByte>& val) = 0;
- virtual void setVecLane(const RegId& reg,
- const LaneData<LaneSize::EightByte>& val) = 0;
- /** @} */
-
virtual const TheISA::VecElem& readVecElem(const RegId& reg) const = 0;
virtual const TheISA::VecPredRegContainer& readVecPredReg(
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idf1d9b68339eb31b95d4a347548240aa9d2a85cc
Gerrit-Change-Number: 41899
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Matthew Poremba <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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