Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41155 )
Change subject: mem-ruby: add wakeup_port statement
......................................................................
mem-ruby: add wakeup_port statement
While the wakeUpBuffers/wakeUpAllBuffers check all message buffers,
wakeup_port wakes up only the messages stalled on the specified port
and address. Usage is the same as the stall_and_wait statement, e.g.:
wakeup_port(reqInPort, addr);
Change-Id: I57dc77d574c0016ca55786ce16a73061a1d37f2e
Signed-off-by: Tiago Mück <tiago.m...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41155
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
Maintainer: Jason Lowe-Power <power...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
A src/mem/slicc/ast/WakeupPortStatementAST.py
M src/mem/slicc/ast/__init__.py
M src/mem/slicc/parser.py
5 files changed, 99 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc
b/src/mem/ruby/slicc_interface/AbstractController.cc
index b7da81e..d39d0fb 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017,2019,2020 ARM Limited
+ * Copyright (c) 2017,2019-2021 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -143,6 +143,28 @@
}
void
+AbstractController::wakeUpBuffer(MessageBuffer* buf, Addr addr)
+{
+ auto iter = m_waiting_buffers.find(addr);
+ if (iter != m_waiting_buffers.end()) {
+ bool has_other_msgs = false;
+ MsgVecType* msgVec = iter->second;
+ for (unsigned int port = 0; port < msgVec->size(); ++port) {
+ if ((*msgVec)[port] == buf) {
+ buf->reanalyzeMessages(addr, clockEdge());
+ (*msgVec)[port] = NULL;
+ } else if ((*msgVec)[port] != NULL) {
+ has_other_msgs = true;
+ }
+ }
+ if (!has_other_msgs) {
+ delete msgVec;
+ m_waiting_buffers.erase(iter);
+ }
+ }
+}
+
+void
AbstractController::wakeUpBuffers(Addr addr)
{
if (m_waiting_buffers.count(addr) > 0) {
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 78ea38c..214b072 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017,2019,2020 ARM Limited
+ * Copyright (c) 2017,2019-2021 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -270,6 +270,7 @@
}
void stallBuffer(MessageBuffer* buf, Addr addr);
+ void wakeUpBuffer(MessageBuffer* buf, Addr addr);
void wakeUpBuffers(Addr addr);
void wakeUpAllBuffers(Addr addr);
void wakeUpAllBuffers();
diff --git a/src/mem/slicc/ast/WakeupPortStatementAST.py
b/src/mem/slicc/ast/WakeupPortStatementAST.py
new file mode 100644
index 0000000..cea3d32
--- /dev/null
+++ b/src/mem/slicc/ast/WakeupPortStatementAST.py
@@ -0,0 +1,55 @@
+# Copyright (c) 2021 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from slicc.ast.StatementAST import StatementAST
+
+class WakeupPortStatementAST(StatementAST):
+ def __init__(self, slicc, in_port, address):
+ super(StatementAST, self).__init__(slicc)
+ self.in_port = in_port
+ self.address = address
+
+ def __repr__(self):
+ return "[WakeupPortStatementAst: %r]" % self.in_port
+
+ def generate(self, code, return_type):
+ self.in_port.assertType("InPort")
+ self.address.assertType("Addr")
+
+ in_port_code = self.in_port.var.code
+ address_code = self.address.var.code
+ code('''
+ wakeUpBuffer(&($in_port_code), $address_code);
+ ''')
diff --git a/src/mem/slicc/ast/__init__.py b/src/mem/slicc/ast/__init__.py
index c410104..247546f 100644
--- a/src/mem/slicc/ast/__init__.py
+++ b/src/mem/slicc/ast/__init__.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2021 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2009 The Hewlett-Packard Development Company
# All rights reserved.
#
@@ -60,6 +72,7 @@
from slicc.ast.PeekStatementAST import *
from slicc.ast.ReturnStatementAST import *
from slicc.ast.StallAndWaitStatementAST import *
+from slicc.ast.WakeupPortStatementAST import *
from slicc.ast.StateDeclAST import *
from slicc.ast.StatementAST import *
from slicc.ast.StatementListAST import *
diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py
index 51a68d0..73ca835 100644
--- a/src/mem/slicc/parser.py
+++ b/src/mem/slicc/parser.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2020 ARM Limited
+# Copyright (c) 2020,2021 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -118,6 +118,7 @@
'state_declaration' : 'STATE_DECL',
'peek' : 'PEEK',
'stall_and_wait' : 'STALL_AND_WAIT',
+ 'wakeup_port' : 'WAKEUP_PORT',
'enqueue' : 'ENQUEUE',
'check_allocate' : 'CHECK_ALLOCATE',
'check_next_cycle' : 'CHECK_NEXT_CYCLE',
@@ -616,6 +617,10 @@
"statement : STALL_AND_WAIT '(' var ',' var ')' SEMI"
p[0] = ast.StallAndWaitStatementAST(self, p[3], p[5])
+ def p_statement__wakeup_port(self, p):
+ "statement : WAKEUP_PORT '(' var ',' var ')' SEMI"
+ p[0] = ast.WakeupPortStatementAST(self, p[3], p[5])
+
def p_statement__peek(self, p):
"statement : PEEK '(' var ',' type pairs ')' statements"
p[0] = ast.PeekStatementAST(self, p[3], p[5], p[6], p[8], "peek")
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I57dc77d574c0016ca55786ce16a73061a1d37f2e
Gerrit-Change-Number: 41155
Gerrit-PatchSet: 3
Gerrit-Owner: Tiago Mück <tiago.m...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Matt Sinclair <mattdsincl...@gmail.com>
Gerrit-Reviewer: Tiago Mück <tiago.m...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: merged
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