Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40178 )
Change subject: arch: Eliminate the GuestByteOrder constant.
......................................................................
arch: Eliminate the GuestByteOrder constant.
Most ISAs used that constant exactly once, when setting up a Process.
This change just propogates the constant to the one place it's used. In
MIPS, the endianness is hard coded as little. There were some checks
which would change the behavior if the endianness was big. This change
removes that dead code. If someone wants to add support for big endian
MIPS, they can go back and add in the small bits of code that would be
required. It's likely the existing big endian support was incomplete and
not tested, so it's probably best for someone interested in it to start
fresh anyway.
Change-Id: Ife6ffcf4bca40001d5d9126f7d795f954f66bb22
---
M src/arch/arm/isa_traits.hh
M src/arch/arm/process.cc
M src/arch/mips/isa/decoder.isa
M src/arch/mips/isa/formats/mem.isa
M src/arch/mips/isa_traits.hh
M src/arch/mips/process.cc
M src/arch/power/isa_traits.hh
M src/arch/power/process.cc
M src/arch/riscv/isa_traits.hh
M src/arch/riscv/process.cc
M src/arch/sparc/isa_traits.hh
M src/arch/sparc/process.cc
M src/arch/x86/isa_traits.hh
M src/arch/x86/process.cc
14 files changed, 11 insertions(+), 32 deletions(-)
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index d8ef5e7..6f6fc9b 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -43,12 +43,9 @@
#define __ARCH_ARM_ISA_TRAITS_HH__
#include "base/types.hh"
-#include "sim/byteswap.hh"
namespace ArmISA
{
- const ByteOrder GuestByteOrder = ByteOrder::little;
-
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
} // namespace ArmISA
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 86bc8e2..757c85a 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -425,7 +425,7 @@
//Copy the aux stuff
Addr auxv_array_end = auxv_array_base;
for (const auto &aux: auxv) {
- initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
+ initVirtMem->write(auxv_array_end, aux, ByteOrder::little);
auxv_array_end += sizeof(aux);
}
//Write out the terminating zeroed auxillary vector
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index e5613f5..ea2b43a 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -1532,10 +1532,7 @@
if (Rs<2:0> == 0) {
Fd_ud = Fs_ud;
} else if (Rs<2:0> == 4) {
- if (GuestByteOrder == ByteOrder::big)
- Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>;
- else
- Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>;
+ Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>;
} else {
Fd_ud = Fd_ud;
}
diff --git a/src/arch/mips/isa/formats/mem.isa
b/src/arch/mips/isa/formats/mem.isa
index ac56803..267d5e8 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -498,8 +498,6 @@
uint32_t mem_word = Mem_uw;
uint32_t unalign_addr = Rs + disp;
uint32_t byte_offset = unalign_addr & 3;
- if (GuestByteOrder == ByteOrder::big)
- byte_offset ^= 3;
'''
memacc_code = decl_code + memacc_code
@@ -516,8 +514,6 @@
uint32_t mem_word = 0;
uint32_t unaligned_addr = Rs + disp;
uint32_t byte_offset = unaligned_addr & 3;
- if (GuestByteOrder == ByteOrder::big)
- byte_offset ^= 3;
fault = readMemAtomicLE(xc, traceData, EA, mem_word,
memAccessFlags);
'''
memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index cf83d74..de21a36 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -31,13 +31,10 @@
#define __ARCH_MIPS_ISA_TRAITS_HH__
#include "base/types.hh"
-#include "sim/byteswap.hh"
namespace MipsISA
{
-const ByteOrder GuestByteOrder = ByteOrder::little;
-
const Addr PageShift = 13;
const Addr PageBytes = ULL(1) << PageShift;
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index e2f2bb9..0439d09 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -37,6 +37,7 @@
#include "mem/page_table.hh"
#include "params/Process.hh"
#include "sim/aux_vector.hh"
+#include "sim/byteswap.hh"
#include "sim/process.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
@@ -184,7 +185,7 @@
// Copy the aux vector
Addr auxv_array_end = auxv_array_base;
for (const auto &aux: auxv) {
- initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
+ initVirtMem->write(auxv_array_end, aux, ByteOrder::little);
auxv_array_end += sizeof(aux);
}
diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh
index fd230eb..0149eec 100644
--- a/src/arch/power/isa_traits.hh
+++ b/src/arch/power/isa_traits.hh
@@ -32,13 +32,10 @@
#define __ARCH_POWER_ISA_TRAITS_HH__
#include "base/types.hh"
-#include "sim/byteswap.hh"
namespace PowerISA
{
-const ByteOrder GuestByteOrder = ByteOrder::big;
-
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc
index 26d28a8..5cdd299 100644
--- a/src/arch/power/process.cc
+++ b/src/arch/power/process.cc
@@ -39,6 +39,7 @@
#include "mem/page_table.hh"
#include "params/Process.hh"
#include "sim/aux_vector.hh"
+#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
#include "sim/system.hh"
@@ -251,7 +252,7 @@
//Copy the aux stuff
Addr auxv_array_end = auxv_array_base;
for (const auto &aux: auxv) {
- initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
+ initVirtMem->write(auxv_array_end, aux, ByteOrder::big);
auxv_array_end += sizeof(aux);
}
//Write out the terminating zeroed auxilliary vector
diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index ee6d8f7..172c557 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -43,13 +43,10 @@
#define __ARCH_RISCV_ISA_TRAITS_HH__
#include "base/types.hh"
-#include "sim/byteswap.hh"
namespace RiscvISA
{
-const ByteOrder GuestByteOrder = ByteOrder::little;
-
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 6718b05..edfbf4b 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -198,7 +198,7 @@
Addr sp = memState->getStackMin();
const auto pushOntoStack =
[this, &sp](IntType data) {
- initVirtMem->write(sp, data, GuestByteOrder);
+ initVirtMem->write(sp, data, ByteOrder::little);
sp += sizeof(data);
};
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index c1690dd..080b4a6 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -30,13 +30,10 @@
#define __ARCH_SPARC_ISA_TRAITS_HH__
#include "base/types.hh"
-#include "sim/byteswap.hh"
namespace SparcISA
{
-const ByteOrder GuestByteOrder = ByteOrder::big;
-
const Addr PageShift = 13;
const Addr PageBytes = ULL(1) << PageShift;
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index 0923eeb..15c4f79 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -41,6 +41,7 @@
#include "mem/page_table.hh"
#include "params/Process.hh"
#include "sim/aux_vector.hh"
+#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
#include "sim/system.hh"
@@ -325,7 +326,7 @@
// Copy the aux stuff
Addr auxv_array_end = auxv_array_base;
for (const auto &aux: auxv) {
- initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
+ initVirtMem->write(auxv_array_end, aux, ByteOrder::big);
auxv_array_end += sizeof(aux);
}
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index befadab..2ab93d8 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -39,12 +39,9 @@
#define __ARCH_X86_ISATRAITS_HH__
#include "base/types.hh"
-#include "sim/byteswap.hh"
namespace X86ISA
{
- const ByteOrder GuestByteOrder = ByteOrder::little;
-
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
}
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 925c836..c6cde4f 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -60,6 +60,7 @@
#include "mem/page_table.hh"
#include "params/Process.hh"
#include "sim/aux_vector.hh"
+#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_desc.hh"
#include "sim/syscall_return.hh"
@@ -959,7 +960,7 @@
// Copy the aux stuff
Addr auxv_array_end = auxv_array_base;
for (const auto &aux: auxv) {
- initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
+ initVirtMem->write(auxv_array_end, aux, ByteOrder::little);
auxv_array_end += sizeof(aux);
}
// Write out the terminating zeroed auxiliary vector
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40178
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ife6ffcf4bca40001d5d9126f7d795f954f66bb22
Gerrit-Change-Number: 40178
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
