Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39855 )
Change subject: arch,base,mem,sim: Fix style in base/types.hh and remove
extra includes.
......................................................................
arch,base,mem,sim: Fix style in base/types.hh and remove extra includes.
The base/refcnt.hh header was not used in base/types.hh at all, and
enum/ByteOrder.hh was there just so other files could find it. Instead,
this change moves enum/Byteorder.hh to sim/byteswap.hh where it's fits
with the purpose of the header.
This change also fixes some style problems with the code in
base/types.hh itself.
Change-Id: I471ae5cb2cca9169ba8616fb8411b40108a3ffb2
---
M src/arch/arm/freebsd/freebsd.hh
M src/arch/arm/isa_traits.hh
M src/arch/mips/isa_traits.hh
M src/arch/power/isa_traits.hh
M src/arch/riscv/isa_traits.hh
M src/arch/sparc/isa_traits.hh
M src/arch/sparc/solaris/solaris.hh
M src/arch/x86/isa_traits.hh
M src/base/pixel.hh
M src/base/types.hh
M src/mem/packet.hh
M src/sim/byteswap.hh
12 files changed, 36 insertions(+), 19 deletions(-)
diff --git a/src/arch/arm/freebsd/freebsd.hh
b/src/arch/arm/freebsd/freebsd.hh
index ef9da65..23fa0af 100644
--- a/src/arch/arm/freebsd/freebsd.hh
+++ b/src/arch/arm/freebsd/freebsd.hh
@@ -34,6 +34,7 @@
#define __ARCH_ARM_FREEBSD_FREEBSD_HH__
#include "kern/freebsd/freebsd.hh"
+#include "sim/byteswap.hh"
class ArmFreebsd : public FreeBSD
{
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index 798db72..d8ef5e7 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -43,6 +43,7 @@
#define __ARCH_ARM_ISA_TRAITS_HH__
#include "base/types.hh"
+#include "sim/byteswap.hh"
namespace ArmISA
{
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index aac595a..cf83d74 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -31,6 +31,7 @@
#define __ARCH_MIPS_ISA_TRAITS_HH__
#include "base/types.hh"
+#include "sim/byteswap.hh"
namespace MipsISA
{
diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh
index 4cf0c44..fd230eb 100644
--- a/src/arch/power/isa_traits.hh
+++ b/src/arch/power/isa_traits.hh
@@ -32,6 +32,7 @@
#define __ARCH_POWER_ISA_TRAITS_HH__
#include "base/types.hh"
+#include "sim/byteswap.hh"
namespace PowerISA
{
diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index 4cf455d..ee6d8f7 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -43,6 +43,7 @@
#define __ARCH_RISCV_ISA_TRAITS_HH__
#include "base/types.hh"
+#include "sim/byteswap.hh"
namespace RiscvISA
{
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 3f7cdac..c1690dd 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -30,6 +30,7 @@
#define __ARCH_SPARC_ISA_TRAITS_HH__
#include "base/types.hh"
+#include "sim/byteswap.hh"
namespace SparcISA
{
diff --git a/src/arch/sparc/solaris/solaris.hh
b/src/arch/sparc/solaris/solaris.hh
index 0462832..7a5aaaf 100644
--- a/src/arch/sparc/solaris/solaris.hh
+++ b/src/arch/sparc/solaris/solaris.hh
@@ -30,6 +30,7 @@
#define __ARCH_SPARC_SOLARIS_SOLARIS_HH__
#include "kern/solaris/solaris.hh"
+#include "sim/byteswap.hh"
class SparcSolaris : public Solaris
{
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index dee98dc..befadab 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -39,6 +39,7 @@
#define __ARCH_X86_ISATRAITS_HH__
#include "base/types.hh"
+#include "sim/byteswap.hh"
namespace X86ISA
{
diff --git a/src/base/pixel.hh b/src/base/pixel.hh
index 7937e89..3cca761 100644
--- a/src/base/pixel.hh
+++ b/src/base/pixel.hh
@@ -47,6 +47,7 @@
#include "base/cprintf.hh"
#include "base/str.hh"
#include "base/types.hh"
+#include "sim/byteswap.hh"
/**
* Internal gem5 representation of a Pixel.
diff --git a/src/base/types.hh b/src/base/types.hh
index 7ae573d..0b93073 100644
--- a/src/base/types.hh
+++ b/src/base/types.hh
@@ -42,10 +42,6 @@
#include <ostream>
#include <stdexcept>
-#include "base/refcnt.hh"
-/* Hide the fact that this enum is generated by Python */
-#include "enums/ByteOrder.hh"
-
/** uint64_t constant */
#define ULL(N) ((uint64_t)N##ULL)
/** int64_t constant */
@@ -100,35 +96,45 @@
constexpr operator uint64_t() const { return c; }
/** Prefix increment operator. */
- Cycles& operator++()
- { ++c; return *this; }
+ Cycles& operator++() { ++c; return *this; }
/** Prefix decrement operator. Is only temporarily used in the O3 CPU.
*/
- Cycles& operator--()
- { assert(c != 0); --c; return *this; }
+ Cycles& operator--() { assert(c != 0); --c; return *this; }
/** In-place addition of cycles. */
- Cycles& operator+=(const Cycles& cc)
- { c += cc.c; return *this; }
+ Cycles& operator+=(const Cycles& cc) { c += cc.c; return *this; }
/** Greater than comparison used for > Cycles(0). */
- constexpr bool operator>(const Cycles& cc) const
- { return c > cc.c; }
+ constexpr bool
+ operator>(const Cycles& cc) const
+ {
+ return c > cc.c;
+ }
- constexpr Cycles operator +(const Cycles& b) const
- { return Cycles(c + b.c); }
+ constexpr Cycles
+ operator+(const Cycles& b) const
+ {
+ return Cycles(c + b.c);
+ }
- constexpr Cycles operator -(const Cycles& b) const
+ constexpr Cycles
+ operator-(const Cycles& b) const
{
return c >= b.c ? Cycles(c - b.c) :
throw std::invalid_argument("RHS cycle value larger than LHS");
}
- constexpr Cycles operator <<(const int32_t shift) const
- { return Cycles(c << shift); }
+ constexpr Cycles
+ operator <<(const int32_t shift) const
+ {
+ return Cycles(c << shift);
+ }
- constexpr Cycles operator >>(const int32_t shift) const
- { return Cycles(c >> shift); }
+ constexpr Cycles
+ operator >>(const int32_t shift) const
+ {
+ return Cycles(c >> shift);
+ }
friend std::ostream& operator<<(std::ostream &out, const Cycles &
cycles);
};
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 0f14816..4ad8d46 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -60,6 +60,7 @@
#include "base/types.hh"
#include "mem/htm.hh"
#include "mem/request.hh"
+#include "sim/byteswap.hh"
#include "sim/core.hh"
class Packet;
diff --git a/src/sim/byteswap.hh b/src/sim/byteswap.hh
index fbe0302..35857a0 100644
--- a/src/sim/byteswap.hh
+++ b/src/sim/byteswap.hh
@@ -35,6 +35,7 @@
#include "base/logging.hh"
#include "base/types.hh"
+#include "enums/ByteOrder.hh"
// This lets us figure out what the byte order of the host system is
#if defined(__linux__)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I471ae5cb2cca9169ba8616fb8411b40108a3ffb2
Gerrit-Change-Number: 39855
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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