Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39676 )
Change subject: cpu: Style fixes in cpu/reg_class.hh.
......................................................................
cpu: Style fixes in cpu/reg_class.hh.
Change-Id: Ie8815c6351609dc9fba9d485e9496b7f7c8ce927
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39676
Reviewed-by: Bobby R. Bruce <bbr...@ucdavis.edu>
Reviewed-by: Daniel Carvalho <oda...@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbr...@ucdavis.edu>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/cpu/reg_class.hh
1 file changed, 44 insertions(+), 35 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 356caf3..d48e700 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -72,7 +72,8 @@
* between different classes of registers. For example, a integer register
with
* index 3 is represented by Regid(IntRegClass, 3).
*/
-class RegId {
+class RegId
+{
protected:
static const char* regClassStrings[];
RegClass regClass;
@@ -91,7 +92,8 @@
explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex
elem_idx)
: regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx),
- numPinnedWrites(0) {
+ numPinnedWrites(0)
+ {
if (elemIdx == ILLEGAL_ELEM_INDEX) {
panic_if(regClass == VecElemClass,
"Creating vector physical index w/o element index");
@@ -101,19 +103,21 @@
}
}
- bool operator==(const RegId& that) const {
- return regClass == that.classValue() && regIdx == that.index()
- && elemIdx ==
that.elemIndex();
+ bool
+ operator==(const RegId& that) const
+ {
+ return regClass == that.classValue() && regIdx == that.index() &&
+ elemIdx == that.elemIndex();
}
- bool operator!=(const RegId& that) const {
- return !(*this==that);
- }
+ bool operator!=(const RegId& that) const { return !(*this==that); }
/** Order operator.
* The order is required to implement maps with key type RegId
*/
- bool operator<(const RegId& that) const {
+ bool
+ operator<(const RegId& that) const
+ {
return regClass < that.classValue() ||
(regClass == that.classValue() && (
regIdx < that.index() ||
@@ -123,7 +127,8 @@
/**
* Return true if this register can be renamed
*/
- bool isRenameable() const
+ bool
+ isRenameable() const
{
return regClass != MiscRegClass;
}
@@ -134,7 +139,8 @@
* constant zero value throughout the execution).
*/
- inline bool isZeroReg() const
+ inline bool
+ isZeroReg() const
{
return regClass == IntRegClass && regIdx == TheISA::ZeroReg;
}
@@ -160,14 +166,6 @@
/** @Return true if it is a condition-code physical register. */
bool isMiscReg() const { return regClass == MiscRegClass; }
- /**
- * Return true if this register can be renamed
- */
- bool isRenameable()
- {
- return regClass != MiscRegClass;
- }
-
/** Index accessors */
/** @{ */
const RegIndex& index() const { return regIdx; }
@@ -176,7 +174,8 @@
/** Index flattening.
* Required to be able to use a vector for the register mapping.
*/
- inline RegIndex flatIndex() const
+ inline RegIndex
+ flatIndex() const
{
switch (regClass) {
case IntRegClass:
@@ -187,7 +186,7 @@
case MiscRegClass:
return regIdx;
case VecElemClass:
- return Scale*regIdx + elemIdx;
+ return Scale * regIdx + elemIdx;
}
panic("Trying to flatten a register without class!");
return -1;
@@ -205,7 +204,8 @@
void setNumPinnedWrites(int num_writes) { numPinnedWrites =
num_writes; }
friend std::ostream&
- operator<<(std::ostream& os, const RegId& rid) {
+ operator<<(std::ostream& os, const RegId& rid)
+ {
return os << rid.className() << "{" << rid.index() << "}";
}
};
@@ -220,7 +220,8 @@
* Like a register ID but physical. The inheritance is private because the
* only relationship between this types is functional, and it is done to
* prevent code replication. */
-class PhysRegId : private RegId {
+class PhysRegId : private RegId
+{
private:
PhysRegIndex flatIdx;
int numPinnedWritesToComplete;
@@ -258,15 +259,21 @@
* RegIds.
*/
/** @{ */
- bool operator<(const PhysRegId& that) const {
+ bool
+ operator<(const PhysRegId& that) const
+ {
return RegId::operator<(that);
}
- bool operator==(const PhysRegId& that) const {
+ bool
+ operator==(const PhysRegId& that) const
+ {
return RegId::operator==(that);
}
- bool operator!=(const PhysRegId& that) const {
+ bool
+ operator!=(const PhysRegId& that) const
+ {
return RegId::operator!=(that);
}
/** @} */
@@ -296,15 +303,13 @@
* Returns true if this register is always associated to the same
* architectural register.
*/
- bool isFixedMapping() const
- {
- return !isRenameable();
- }
+ bool isFixedMapping() const { return !isRenameable(); }
/** Flat index accessor */
const PhysRegIndex& flatIndex() const { return flatIdx; }
- static PhysRegId elemId(PhysRegId* vid, ElemIndex elem)
+ static PhysRegId
+ elemId(PhysRegId* vid, ElemIndex elem)
{
assert(vid->isVectorPhysReg());
return PhysRegId(VecElemClass, vid->index(), elem);
@@ -312,7 +317,8 @@
int getNumPinnedWrites() const { return numPinnedWrites; }
- void setNumPinnedWrites(int numWrites)
+ void
+ setNumPinnedWrites(int numWrites)
{
// An instruction with a pinned destination reg can get
// squashed. The numPinnedWrites counter may be zero when
@@ -329,12 +335,14 @@
bool isPinned() const { return pinned; }
- int getNumPinnedWritesToComplete() const
+ int
+ getNumPinnedWritesToComplete() const
{
return numPinnedWritesToComplete;
}
- void setNumPinnedWritesToComplete(int numWrites)
+ void
+ setNumPinnedWritesToComplete(int numWrites)
{
numPinnedWritesToComplete = numWrites;
}
@@ -350,7 +358,8 @@
template<>
struct hash<RegId>
{
- size_t operator()(const RegId& reg_id) const
+ size_t
+ operator()(const RegId& reg_id) const
{
// Extract unique integral values for the effective fields of a
RegId.
const size_t flat_index = static_cast<size_t>(reg_id.flatIndex());
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie8815c6351609dc9fba9d485e9496b7f7c8ce927
Gerrit-Change-Number: 39676
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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