[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Move getExecutingAsid to the ISA class.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39322 )

Change subject: arch,cpu: Move getExecutingAsid to the ISA class.
......................................................................

arch,cpu: Move getExecutingAsid to the ISA class.

This function was switched based on the ISA, and returned 0 on
everything except SPARC and ARM. It was used only when tracing
instruction execution with --debug-flags=Exec.

Change-Id: I70c274cb76fb229d0e2bc606ba41f458ed18ab81
---
M src/arch/arm/isa.hh
M src/arch/arm/utility.hh
M src/arch/generic/isa.hh
M src/arch/mips/utility.hh
M src/arch/power/utility.hh
M src/arch/riscv/utility.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/utility.hh
M src/arch/x86/utility.hh
M src/cpu/exetrace.cc
10 files changed, 14 insertions(+), 38 deletions(-)



diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index dce5e37..97b41cc 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -886,6 +886,12 @@
         const Params &params() const;

         ISA(const Params &p);
+
+        uint64_t
+        getExecutingAsid() const override
+        {
+            return readMiscRegNoEffect(MISCREG_CONTEXTIDR);
+        }
     };
 }

diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index fcaefbb..e255b1c 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -409,12 +409,6 @@
 Addr truncPage(Addr addr);
 Addr roundPage(Addr addr);

-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-    return tc->readMiscReg(MISCREG_CONTEXTIDR);
-}
-
 // Decodes the register index to access based on the fields used in a MSR
 // or MRS instruction
 bool
diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index df07763..9ea2d9f 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -57,6 +57,8 @@
     {}

     virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
+
+    virtual uint64_t getExecutingAsid() const { return 0; }
 };

 #endif // __ARCH_GENERIC_ISA_HH__
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index a0d222e..0cb9349 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -106,12 +106,6 @@
     pc.advance();
 }

-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-    return 0;
-}
-
 };


diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index 80b98c6..9092a23 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -64,12 +64,6 @@
     return 0;
 }

-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-    return 0;
-}
-
 } // namespace PowerISA


diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index 1f82d2b..c2f4ac8 100644
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -163,12 +163,6 @@
     return true;
 }

-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-    return 0;
-}
-
 } // namespace RiscvISA

 #endif // __ARCH_RISCV_UTILITY_HH__
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 2881384..21143dd 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -215,6 +215,11 @@
     int flattenCCIndex(int reg) const { return reg; }
     int flattenMiscIndex(int reg) const { return reg; }

+    uint64_t
+    getExecutingAsid() const override
+    {
+        return readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT);
+    }

     typedef SparcISAParams Params;
     const Params &params() const;
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 8a638e1..18b5164 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -68,12 +68,6 @@
     inst->advancePC(pc);
 }

-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
-    return tc->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT);
-}
-
 } // namespace SparcISA

 #endif
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 4ae8102..1ff7b16 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -74,13 +74,6 @@
         inst->advancePC(pc);
     }

-    inline uint64_t
-    getExecutingAsid(ThreadContext *tc)
-    {
-        return 0;
-    }
-
-
     /**
      * Reconstruct the rflags register from the internal gem5 register
      * state.
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 4980c91..17c877e 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -70,7 +70,7 @@
     }

     if (Debug::ExecAsid)
-        outs << "A" << dec << TheISA::getExecutingAsid(thread) << " ";
+        outs << "A" << dec << thread->getIsaPtr()->getExecutingAsid()  
<< " ";

     if (Debug::ExecThread)
         outs << "T" << thread->threadId() << " : ";

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I70c274cb76fb229d0e2bc606ba41f458ed18ab81
Gerrit-Change-Number: 39322
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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