Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27791 )
Change subject: arm: Use the common pseudoInst dispatch function.
......................................................................
arm: Use the common pseudoInst dispatch function.
Instead of manually calling each of the PseudoInst implementations, this
function will automatically pick up new instructions and greatly
simplifies the ARM ISA files.
Change-Id: I6cb94b3d115f50d681ca855f80f9d7d3df6bc470
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27791
Reviewed-by: Bobby R. Bruce <[email protected]>
Maintainer: Giacomo Travaglini <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/isa/decoder/arm.isa
M src/arch/arm/isa/decoder/thumb.isa
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/formats.isa
D src/arch/arm/isa/formats/m5ops.isa
M src/arch/arm/isa/formats/misc.isa
M src/arch/arm/isa/insts/m5ops.isa
7 files changed, 32 insertions(+), 682 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa/decoder/arm.isa
b/src/arch/arm/isa/decoder/arm.isa
index 838e27b..0349b39 100644
--- a/src/arch/arm/isa/decoder/arm.isa
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -119,7 +119,7 @@
0xa, 0xb: VfpData::vfpData();
} // CPNUM
1: decode CPNUM { // 27-24=1110,4 ==1
- 0x1: M5ops::m5ops();
+ 0x1: Gem5Op::gem5op();
0xa, 0xb: ShortFpTransfer::shortFpTransfer();
0xe: McrMrc14::mcrMrc14();
0xf: McrMrc15::mcrMrc15();
diff --git a/src/arch/arm/isa/decoder/thumb.isa
b/src/arch/arm/isa/decoder/thumb.isa
index c319ec3..1509cc3 100644
--- a/src/arch/arm/isa/decoder/thumb.isa
+++ b/src/arch/arm/isa/decoder/thumb.isa
@@ -82,7 +82,7 @@
default: WarnUnimpl::cdp(); // cdp2
}
0x1: decode LTCOPROC {
- 0x1: M5ops::m5ops();
+ 0x1: Gem5Op::gem5op();
0xa, 0xb: ShortFpTransfer::shortFpTransfer();
0xe: McrMrc14::mcrMrc14();
0xf: McrMrc15::mcrMrc15();
@@ -147,7 +147,7 @@
default: WarnUnimpl::cdp(); // cdp2
}
0x1: decode LTCOPROC {
- 0x1: M5ops::m5ops();
+ 0x1: Gem5Op::gem5op();
0xa, 0xb: ShortFpTransfer::shortFpTransfer();
0xe: McrMrc14::mcrMrc14();
0xf: McrMrc15::mcrMrc15();
diff --git a/src/arch/arm/isa/formats/aarch64.isa
b/src/arch/arm/isa/formats/aarch64.isa
index 9a487ea..a873b1e 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -3029,47 +3029,6 @@
}'''
}};
-output decoder {{
-namespace Aarch64
-{
- StaticInstPtr
- decodeGem5Ops(ExtMachInst machInst)
- {
- const uint32_t m5func = bits(machInst, 23, 16);
- switch (m5func) {
- case M5OP_ARM: return new Arm(machInst);
- case M5OP_QUIESCE: return new Quiesce(machInst);
- case M5OP_QUIESCE_NS: return new QuiesceNs64(machInst);
- case M5OP_QUIESCE_CYCLE: return new QuiesceCycles64(machInst);
- case M5OP_QUIESCE_TIME: return new QuiesceTime64(machInst);
- case M5OP_RPNS: return new Rpns64(machInst);
- case M5OP_WAKE_CPU: return new WakeCPU64(machInst);
- case M5OP_DEPRECATED1: return new Deprecated_ivlb(machInst);
- case M5OP_DEPRECATED2: return new Deprecated_ivle(machInst);
- case M5OP_DEPRECATED3: return new Deprecated_exit (machInst);
- case M5OP_EXIT: return new M5exit64(machInst);
- case M5OP_FAIL: return new M5fail64(machInst);
- case M5OP_SUM: return new M5sum64(machInst);
- case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst);
- case M5OP_INIT_PARAM: return new Initparam64(machInst);
- case M5OP_RESET_STATS: return new Resetstats64(machInst);
- case M5OP_DUMP_STATS: return new Dumpstats64(machInst);
- case M5OP_DUMP_RESET_STATS: return new
Dumpresetstats64(machInst);
- case M5OP_CHECKPOINT: return new M5checkpoint64(machInst);
- case M5OP_WRITE_FILE: return new M5writefile64(machInst);
- case M5OP_READ_FILE: return new M5readfile64(machInst);
- case M5OP_DEBUG_BREAK: return new M5break(machInst);
- case M5OP_SWITCH_CPU: return new M5switchcpu(machInst);
- case M5OP_ADD_SYMBOL: return new M5addsymbol64(machInst);
- case M5OP_PANIC: return new M5panic(machInst);
- case M5OP_WORK_BEGIN: return new M5workbegin64(machInst);
- case M5OP_WORK_END: return new M5workend64(machInst);
- default: return new Unknown64(machInst);
- }
- }
-}
-}};
-
def format Aarch64() {{
decode_block = '''
{
@@ -3105,7 +3064,7 @@
return decodeDataProcReg(machInst);
} else if (bits(machInst, 24) == 1 &&
bits(machInst, 31, 28) == 0xF) {
- return decodeGem5Ops(machInst);
+ return new Gem5Op64(machInst);
} else {
// bit 27:25=111
switch(decoderFlavor){
diff --git a/src/arch/arm/isa/formats/formats.isa
b/src/arch/arm/isa/formats/formats.isa
index 0c1b217..5ef6596 100644
--- a/src/arch/arm/isa/formats/formats.isa
+++ b/src/arch/arm/isa/formats/formats.isa
@@ -82,9 +82,6 @@
//Unconditional instructions
##include "uncond.isa"
-//M5 Psuedo-ops
-##include "m5ops.isa"
-
//Crypto Ops
##include "crypto64.isa"
diff --git a/src/arch/arm/isa/formats/m5ops.isa
b/src/arch/arm/isa/formats/m5ops.isa
deleted file mode 100644
index 6120644..0000000
--- a/src/arch/arm/isa/formats/m5ops.isa
+++ /dev/null
@@ -1,74 +0,0 @@
-//
-// Copyright (c) 2010 ARM Limited
-// All rights reserved
-//
-// The license below extends only to copyright in the software and shall
-// not be construed as granting a license to any other intellectual
-// property including but not limited to intellectual property relating
-// to a hardware implementation of the functionality of the software
-// licensed hereunder. You may use the software subject to the license
-// terms below provided that you ensure that this notice is replicated
-// unmodified and in its entirety in all distributions of the software,
-// modified or unmodified, in source code or in binary form.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-///
-
-def format M5ops() {{
- decode_block = '''
- {
- const uint32_t m5func = bits(machInst, 23, 16);
- switch(m5func) {
- case M5OP_ARM: return new Arm(machInst);
- case M5OP_QUIESCE: return new Quiesce(machInst);
- case M5OP_QUIESCE_NS: return new QuiesceNs(machInst);
- case M5OP_QUIESCE_CYCLE: return new QuiesceCycles(machInst);
- case M5OP_QUIESCE_TIME: return new QuiesceTime(machInst);
- case M5OP_RPNS: return new Rpns(machInst);
- case M5OP_WAKE_CPU: return new WakeCPU(machInst);
- case M5OP_DEPRECATED1: return new Deprecated_ivlb(machInst);
- case M5OP_DEPRECATED2: return new Deprecated_ivle(machInst);
- case M5OP_DEPRECATED3: return new Deprecated_exit (machInst);
- case M5OP_EXIT: return new M5exit(machInst);
- case M5OP_FAIL: return new M5fail(machInst);
- case M5OP_SUM: return new M5sum(machInst);
- case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst);
- case M5OP_INIT_PARAM: return new Initparam(machInst);
- case M5OP_RESET_STATS: return new Resetstats(machInst);
- case M5OP_DUMP_STATS: return new Dumpstats(machInst);
- case M5OP_DUMP_RESET_STATS: return new
Dumpresetstats(machInst);
- case M5OP_CHECKPOINT: return new M5checkpoint(machInst);
- case M5OP_WRITE_FILE: return new M5writefile(machInst);
- case M5OP_READ_FILE: return new M5readfile(machInst);
- case M5OP_DEBUG_BREAK: return new M5break(machInst);
- case M5OP_SWITCH_CPU: return new M5switchcpu(machInst);
- case M5OP_ADD_SYMBOL: return new M5addsymbol(machInst);
- case M5OP_PANIC: return new M5panic(machInst);
- case M5OP_WORK_BEGIN: return new M5workbegin(machInst);
- case M5OP_WORK_END: return new M5workend(machInst);
- default: return new Unknown(machInst);
- }
- }
- '''
-}};
diff --git a/src/arch/arm/isa/formats/misc.isa
b/src/arch/arm/isa/formats/misc.isa
index 3f74b06..32fccc8 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -352,3 +352,9 @@
return decodeMcrrMrrc15(machInst);
'''
}};
+
+def format Gem5Op() {{
+ decode_block = '''
+ return new Gem5Op(machInst);
+ '''
+}};
diff --git a/src/arch/arm/isa/insts/m5ops.isa
b/src/arch/arm/isa/insts/m5ops.isa
index 3dcec7e..48d533d 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -36,566 +36,28 @@
let {{
- header_output = '''
- uint64_t join32to64(uint32_t r1, uint32_t r0);
+ gem5OpCode = '''
+ uint64_t ret;
+ bool recognized = PseudoInst::pseudoInst<PseudoInstABI>(
+ xc->tcBase(), bits(machInst, 23, 16), ret);
+ if (!recognized)
+ fault = std::make_shared<UndefinedInstruction>(machInst, true);
'''
- decoder_output = '''
- uint64_t join32to64(uint32_t r1, uint32_t r0)
- {
- uint64_t r = r1;
- r <<= 32;
- r |= r0;
- return r;
- }
- '''
- exec_output = '''
- uint64_t join32to64(uint32_t r1, uint32_t r0);
- '''
+ gem5OpIop = InstObjParams("gem5op", "Gem5Op64", "PredOp",
+ { "code": gem5OpCode + 'X0 = ret;',
+ "predicate_test": predicateTest },
+ [ "IsNonSpeculative", "IsUnverifiable" ]);
+ header_output += BasicDeclare.subst(gem5OpIop)
+ decoder_output += BasicConstructor.subst(gem5OpIop)
+ exec_output += PredOpExecute.subst(gem5OpIop)
-
- armCode = '''
- PseudoInst::arm(xc->tcBase());
- '''
-
- armIop = InstObjParams("arm", "Arm", "PredOp",
- { "code": armCode,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(armIop)
- decoder_output += BasicConstructor.subst(armIop)
- exec_output += PredOpExecute.subst(armIop)
-
- quiesceCode = '''
- PseudoInst::quiesce(xc->tcBase());
- '''
-
- quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
- { "code": quiesceCode,
- "predicate_test": predicateTest },
- ["IsNonSpeculative", "IsQuiesce"])
- header_output += BasicDeclare.subst(quiesceIop)
- decoder_output += BasicConstructor.subst(quiesceIop)
- exec_output += QuiescePredOpExecute.subst(quiesceIop)
-
- quiesceNsCode = '''
- PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0));
- '''
-
- quiesceNsCode64 = '''
- PseudoInst::quiesceNs(xc->tcBase(), X0);
- '''
-
- quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp",
- { "code": quiesceNsCode,
- "predicate_test": predicateTest },
- ["IsNonSpeculative", "IsQuiesce"])
- header_output += BasicDeclare.subst(quiesceNsIop)
- decoder_output += BasicConstructor.subst(quiesceNsIop)
- exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
-
- quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs64", "PredOp",
- { "code": quiesceNsCode64,
- "predicate_test": predicateTest },
- ["IsNonSpeculative", "IsQuiesce"])
- header_output += BasicDeclare.subst(quiesceNsIop)
- decoder_output += BasicConstructor.subst(quiesceNsIop)
- exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
-
- quiesceCyclesCode = '''
- PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0));
- '''
-
- quiesceCyclesCode64 = '''
- PseudoInst::quiesceCycles(xc->tcBase(), X0);
- '''
-
- quiesceCyclesIop =
InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp",
- { "code": quiesceCyclesCode,
- "predicate_test": predicateTest },
-
["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"])
- header_output += BasicDeclare.subst(quiesceCyclesIop)
- decoder_output += BasicConstructor.subst(quiesceCyclesIop)
- exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
-
- quiesceCyclesIop =
InstObjParams("quiesceCycles", "QuiesceCycles64", "PredOp",
- { "code": quiesceCyclesCode64,
- "predicate_test": predicateTest },
-
["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"])
- header_output += BasicDeclare.subst(quiesceCyclesIop)
- decoder_output += BasicConstructor.subst(quiesceCyclesIop)
- exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
-
- quiesceTimeCode = '''
- uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase());
- R0 = bits(qt_val, 31, 0);
- R1 = bits(qt_val, 63, 32);
- '''
-
- quiesceTimeCode64 = '''
- X0 = PseudoInst::quiesceTime(xc->tcBase());
- '''
- quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp",
- { "code": quiesceTimeCode,
- "predicate_test": predicateTest },
- ["IsNonSpeculative", "IsUnverifiable"])
- header_output += BasicDeclare.subst(quiesceTimeIop)
- decoder_output += BasicConstructor.subst(quiesceTimeIop)
- exec_output += PredOpExecute.subst(quiesceTimeIop)
-
- quiesceTimeIop =
InstObjParams("quiesceTime", "QuiesceTime64", "PredOp",
- { "code": quiesceTimeCode64,
- "predicate_test": predicateTest },
- ["IsNonSpeculative", "IsUnverifiable"])
- header_output += BasicDeclare.subst(quiesceTimeIop)
- decoder_output += BasicConstructor.subst(quiesceTimeIop)
- exec_output += PredOpExecute.subst(quiesceTimeIop)
-
- rpnsCode = '''
- uint64_t rpns_val = PseudoInst::rpns(xc->tcBase());
- R0 = bits(rpns_val, 31, 0);
- R1 = bits(rpns_val, 63, 32);
- '''
-
- rpnsCode64 = '''
- X0 = PseudoInst::rpns(xc->tcBase());
- '''
- rpnsIop = InstObjParams("rpns", "Rpns", "PredOp",
- { "code": rpnsCode,
- "predicate_test": predicateTest },
- ["IsNonSpeculative", "IsUnverifiable"])
- header_output += BasicDeclare.subst(rpnsIop)
- decoder_output += BasicConstructor.subst(rpnsIop)
- exec_output += PredOpExecute.subst(rpnsIop)
-
- rpnsIop = InstObjParams("rpns", "Rpns64", "PredOp",
- { "code": rpnsCode64,
- "predicate_test": predicateTest },
- ["IsNonSpeculative", "IsUnverifiable"])
- header_output += BasicDeclare.subst(rpnsIop)
- decoder_output += BasicConstructor.subst(rpnsIop)
- exec_output += PredOpExecute.subst(rpnsIop)
-
- wakeCpuCode = '''
- PseudoInst::wakeCPU(xc->tcBase(), join32to64(R1,R0));
- '''
-
- wakeCpuCode64 = '''
- PseudoInst::wakeCPU(xc->tcBase(), X0);
- '''
-
- wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PredOp",
- { "code": wakeCpuCode,
- "predicate_test": predicateTest },
- ["IsNonSpeculative", "IsUnverifiable"])
- header_output += BasicDeclare.subst(wakeCPUIop)
- decoder_output += BasicConstructor.subst(wakeCPUIop)
- exec_output += PredOpExecute.subst(wakeCPUIop)
-
- wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU64", "PredOp",
- { "code": wakeCpuCode64,
- "predicate_test": predicateTest },
- ["IsNonSpeculative", "IsUnverifiable"])
- header_output += BasicDeclare.subst(wakeCPUIop)
- decoder_output += BasicConstructor.subst(wakeCPUIop)
- exec_output += PredOpExecute.subst(wakeCPUIop)
-
- deprecated_ivlbIop =
InstObjParams("deprecated_ivlb", "Deprecated_ivlb", "PredOp",
- { "code": '''warn_once("Obsolete M5 ivlb
instruction encountered.\\n");''',
- "predicate_test": predicateTest })
- header_output += BasicDeclare.subst(deprecated_ivlbIop)
- decoder_output += BasicConstructor.subst(deprecated_ivlbIop)
- exec_output += PredOpExecute.subst(deprecated_ivlbIop)
-
- deprecated_ivleIop =
InstObjParams("deprecated_ivle", "Deprecated_ivle", "PredOp",
- { "code": '''warn_once("Obsolete M5 ivle
instruction encountered.\\n");''',
- "predicate_test": predicateTest })
- header_output += BasicDeclare.subst(deprecated_ivleIop)
- decoder_output += BasicConstructor.subst(deprecated_ivleIop)
- exec_output += PredOpExecute.subst(deprecated_ivleIop)
-
- deprecated_exit_code = '''
- warn_once("Obsolete M5 exit instruction encountered.\\n");
- PseudoInst::m5exit(xc->tcBase(), 0);
- '''
-
- deprecated_exitIop =
InstObjParams("deprecated_exit", "Deprecated_exit", "PredOp",
- { "code": deprecated_exit_code,
- "predicate_test": predicateTest },
- ["No_OpClass", "IsNonSpeculative"])
- header_output += BasicDeclare.subst(deprecated_exitIop)
- decoder_output += BasicConstructor.subst(deprecated_exitIop)
- exec_output += PredOpExecute.subst(deprecated_exitIop)
-
- m5exit_code = '''
- PseudoInst::m5exit(xc->tcBase(), join32to64(R1, R0));
- '''
-
- m5exit_code64 = '''
- PseudoInst::m5exit(xc->tcBase(), X0);
- '''
-
- m5exitIop = InstObjParams("m5exit", "M5exit", "PredOp",
- { "code": m5exit_code,
- "predicate_test": predicateTest },
- ["No_OpClass", "IsNonSpeculative"])
- header_output += BasicDeclare.subst(m5exitIop)
- decoder_output += BasicConstructor.subst(m5exitIop)
- exec_output += PredOpExecute.subst(m5exitIop)
-
- m5fail_code = '''
- PseudoInst::m5fail(xc->tcBase(), join32to64(R1, R0),
join32to64(R3, R2));
- '''
-
- m5fail_code64 = '''
- PseudoInst::m5fail(xc->tcBase(), X0, X1);
- '''
-
- m5failIop = InstObjParams("m5fail", "M5fail", "PredOp",
- { "code": m5fail_code,
- "predicate_test": predicateTest },
- ["No_OpClass", "IsNonSpeculative"])
- header_output += BasicDeclare.subst(m5failIop)
- decoder_output += BasicConstructor.subst(m5failIop)
- exec_output += PredOpExecute.subst(m5failIop)
-
- m5failIop = InstObjParams("m5fail", "M5fail64", "PredOp",
- { "code": m5fail_code64,
- "predicate_test": predicateTest },
- ["No_OpClass", "IsNonSpeculative"])
- header_output += BasicDeclare.subst(m5failIop)
- decoder_output += BasicConstructor.subst(m5failIop)
- exec_output += PredOpExecute.subst(m5failIop)
-
-
- m5exitIop = InstObjParams("m5exit", "M5exit64", "PredOp",
- { "code": m5exit_code64,
- "predicate_test": predicateTest },
- ["No_OpClass", "IsNonSpeculative"])
- header_output += BasicDeclare.subst(m5exitIop)
- decoder_output += BasicConstructor.subst(m5exitIop)
- exec_output += PredOpExecute.subst(m5exitIop)
-
- loadsymbolCode = '''
- PseudoInst::loadsymbol(xc->tcBase());
- '''
-
- m5sum_code = '''
- R0 = PseudoInst::m5sum(xc->tcBase(), R0, R1, R2, R3, R4, R5);
- '''
- m5sumIop = InstObjParams("m5sum", "M5sum", "PredOp",
- { "code": m5sum_code,
- "predicate_test": predicateTest },
- ["No_OpClass", "IsNonSpeculative"])
- header_output += BasicDeclare.subst(m5sumIop)
- decoder_output += BasicConstructor.subst(m5sumIop)
- exec_output += PredOpExecute.subst(m5sumIop)
-
- m5sum_code64 = '''
- X0 = PseudoInst::m5sum(xc->tcBase(), X0, X1, X2, X3, X4, X5);
- '''
- m5sumIop = InstObjParams("m5sum", "M5sum64", "PredOp",
- { "code": m5sum_code64,
- "predicate_test": predicateTest },
- ["No_OpClass", "IsNonSpeculative"])
- header_output += BasicDeclare.subst(m5sumIop)
- decoder_output += BasicConstructor.subst(m5sumIop)
- exec_output += PredOpExecute.subst(m5sumIop)
-
- loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp",
- { "code": loadsymbolCode,
- "predicate_test": predicateTest },
- ["No_OpClass", "IsNonSpeculative"])
- header_output += BasicDeclare.subst(loadsymbolIop)
- decoder_output += BasicConstructor.subst(loadsymbolIop)
- exec_output += PredOpExecute.subst(loadsymbolIop)
-
- initparamCode = '''
- uint64_t ip_val = PseudoInst::initParam(xc->tcBase(), join32to64(R1,
R0),
- join32to64(R3, R2));
- R0 = bits(ip_val, 31, 0);
- R1 = bits(ip_val, 63, 32);
- '''
-
- initparamCode64 = '''
- X0 = PseudoInst::initParam(xc->tcBase(), X0, X1);
- '''
-
- initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
- { "code": initparamCode,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(initparamIop)
- decoder_output += BasicConstructor.subst(initparamIop)
- exec_output += PredOpExecute.subst(initparamIop)
-
- initparamIop = InstObjParams("initparam", "Initparam64", "PredOp",
- { "code": initparamCode64,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(initparamIop)
- decoder_output += BasicConstructor.subst(initparamIop)
- exec_output += PredOpExecute.subst(initparamIop)
-
- resetstats_code = '''
- PseudoInst::resetstats(xc->tcBase(), join32to64(R1, R0),
join32to64(R3, R2));
- '''
-
- resetstats_code64 = '''
- PseudoInst::resetstats(xc->tcBase(), X0, X1);
- '''
- resetstatsIop = InstObjParams("resetstats", "Resetstats", "PredOp",
- { "code": resetstats_code,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(resetstatsIop)
- decoder_output += BasicConstructor.subst(resetstatsIop)
- exec_output += PredOpExecute.subst(resetstatsIop)
-
- resetstatsIop = InstObjParams("resetstats", "Resetstats64", "PredOp",
- { "code": resetstats_code64,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(resetstatsIop)
- decoder_output += BasicConstructor.subst(resetstatsIop)
- exec_output += PredOpExecute.subst(resetstatsIop)
-
- dumpstats_code = '''
- PseudoInst::dumpstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3,
R2));
- '''
-
- dumpstats_code64 = '''
- PseudoInst::dumpstats(xc->tcBase(), X0, X1);
- '''
-
- dumpstatsIop = InstObjParams("dumpstats", "Dumpstats", "PredOp",
- { "code": dumpstats_code,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(dumpstatsIop)
- decoder_output += BasicConstructor.subst(dumpstatsIop)
- exec_output += PredOpExecute.subst(dumpstatsIop)
-
- dumpstatsIop = InstObjParams("dumpstats", "Dumpstats64", "PredOp",
- { "code": dumpstats_code64,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(dumpstatsIop)
- decoder_output += BasicConstructor.subst(dumpstatsIop)
- exec_output += PredOpExecute.subst(dumpstatsIop)
-
- dumpresetstats_code = '''
- PseudoInst::dumpresetstats(xc->tcBase(), join32to64(R1, R0),
join32to64(R3, R2));
- '''
-
- dumpresetstats_code64 = '''
- PseudoInst::dumpresetstats(xc->tcBase(), X0, X1);
- '''
-
- dumpresetstatsIop =
InstObjParams("dumpresetstats", "Dumpresetstats", "PredOp",
- { "code": dumpresetstats_code,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(dumpresetstatsIop)
- decoder_output += BasicConstructor.subst(dumpresetstatsIop)
- exec_output += PredOpExecute.subst(dumpresetstatsIop)
-
- dumpresetstatsIop =
InstObjParams("dumpresetstats", "Dumpresetstats64", "PredOp",
- { "code": dumpresetstats_code64,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(dumpresetstatsIop)
- decoder_output += BasicConstructor.subst(dumpresetstatsIop)
- exec_output += PredOpExecute.subst(dumpresetstatsIop)
-
- m5checkpoint_code = '''
- PseudoInst::m5checkpoint(xc->tcBase(), join32to64(R1, R0),
join32to64(R3, R2));
- '''
-
- m5checkpoint_code64 = '''
- PseudoInst::m5checkpoint(xc->tcBase(), X0, X1);
- '''
-
- m5checkpointIop =
InstObjParams("m5checkpoint", "M5checkpoint", "PredOp",
- { "code": m5checkpoint_code,
- "predicate_test": predicateTest },
- ["IsNonSpeculative", "IsUnverifiable"])
- header_output += BasicDeclare.subst(m5checkpointIop)
- decoder_output += BasicConstructor.subst(m5checkpointIop)
- exec_output += PredOpExecute.subst(m5checkpointIop)
-
- m5checkpointIop =
InstObjParams("m5checkpoint", "M5checkpoint64", "PredOp",
- { "code": m5checkpoint_code64,
- "predicate_test": predicateTest },
- ["IsNonSpeculative", "IsUnverifiable"])
- header_output += BasicDeclare.subst(m5checkpointIop)
- decoder_output += BasicConstructor.subst(m5checkpointIop)
- exec_output += PredOpExecute.subst(m5checkpointIop)
-
- m5readfileCode = '''
- int n = 4;
- uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t),
false);
- R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset);
- '''
-
- m5readfileCode64 = '''
- int n = 2;
- uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t),
false);
- n = 3;
- X0 = PseudoInst::readfile(xc->tcBase(), X0, X1, offset);
- '''
-
- m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
- { "code": m5readfileCode,
- "predicate_test": predicateTest },
- ["IsNonSpeculative", "IsUnverifiable"])
- header_output += BasicDeclare.subst(m5readfileIop)
- decoder_output += BasicConstructor.subst(m5readfileIop)
- exec_output += PredOpExecute.subst(m5readfileIop)
-
- m5readfileIop = InstObjParams("m5readfile", "M5readfile64", "PredOp",
- { "code": m5readfileCode64,
- "predicate_test": predicateTest },
- ["IsNonSpeculative", "IsUnverifiable"])
- header_output += BasicDeclare.subst(m5readfileIop)
- decoder_output += BasicConstructor.subst(m5readfileIop)
- exec_output += PredOpExecute.subst(m5readfileIop)
-
- m5writefileCode = '''
- int n = 4;
- uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t),
false);
- n = 6;
- Addr filenameAddr = getArgument(xc->tcBase(), n, sizeof(Addr), false);
- R0 = PseudoInst::writefile(xc->tcBase(), R0, join32to64(R3,R2), offset,
- filenameAddr);
- '''
-
- m5writefileCode64 = '''
- int n = 2;
- uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t),
false);
- n = 3;
- Addr filenameAddr = getArgument(xc->tcBase(), n, sizeof(Addr), false);
- X0 = PseudoInst::writefile(xc->tcBase(), X0, X1, offset,
- filenameAddr);
- '''
-
- m5writefileIop = InstObjParams("m5writefile", "M5writefile", "PredOp",
- { "code": m5writefileCode,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(m5writefileIop)
- decoder_output += BasicConstructor.subst(m5writefileIop)
- exec_output += PredOpExecute.subst(m5writefileIop)
-
- m5writefileIop =
InstObjParams("m5writefile", "M5writefile64", "PredOp",
- { "code": m5writefileCode64,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(m5writefileIop)
- decoder_output += BasicConstructor.subst(m5writefileIop)
- exec_output += PredOpExecute.subst(m5writefileIop)
-
- m5breakIop = InstObjParams("m5break", "M5break", "PredOp",
-
{ "code": "PseudoInst::debugbreak(xc->tcBase());",
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(m5breakIop)
- decoder_output += BasicConstructor.subst(m5breakIop)
- exec_output += PredOpExecute.subst(m5breakIop)
-
- m5switchcpuIop = InstObjParams("m5switchcpu", "M5switchcpu", "PredOp",
-
{ "code": "PseudoInst::switchcpu(xc->tcBase());",
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(m5switchcpuIop)
- decoder_output += BasicConstructor.subst(m5switchcpuIop)
- exec_output += PredOpExecute.subst(m5switchcpuIop)
-
- m5addsymbolCode = '''
- PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2);
- '''
- m5addsymbolCode64 = '''
- PseudoInst::addsymbol(xc->tcBase(), X0, X1);
- '''
- m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp",
- { "code": m5addsymbolCode,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(m5addsymbolIop)
- decoder_output += BasicConstructor.subst(m5addsymbolIop)
- exec_output += PredOpExecute.subst(m5addsymbolIop)
-
- m5addsymbolIop =
InstObjParams("m5addsymbol", "M5addsymbol64", "PredOp",
- { "code": m5addsymbolCode64,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(m5addsymbolIop)
- decoder_output += BasicConstructor.subst(m5addsymbolIop)
- exec_output += PredOpExecute.subst(m5addsymbolIop)
-
- m5panicCode = '''panic("M5 panic instruction called at pc=%#x.",
- xc->pcState().pc());'''
-
- m5panicIop = InstObjParams("m5panic", "M5panic", "PredOp",
- { "code": m5panicCode,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(m5panicIop)
- decoder_output += BasicConstructor.subst(m5panicIop)
- exec_output += PredOpExecute.subst(m5panicIop)
-
- m5workbeginCode = '''PseudoInst::workbegin(
- xc->tcBase(),
- join32to64(R1, R0),
- join32to64(R3, R2)
- );'''
-
- m5workbeginCode64 = '''PseudoInst::workbegin(
- xc->tcBase(),
- X0,
- X1
- );'''
-
- m5workbeginIop = InstObjParams("m5workbegin", "M5workbegin", "PredOp",
- { "code": m5workbeginCode,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(m5workbeginIop)
- decoder_output += BasicConstructor.subst(m5workbeginIop)
- exec_output += PredOpExecute.subst(m5workbeginIop)
-
- m5workbeginIop =
InstObjParams("m5workbegin", "M5workbegin64", "PredOp",
- { "code": m5workbeginCode64,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(m5workbeginIop)
- decoder_output += BasicConstructor.subst(m5workbeginIop)
- exec_output += PredOpExecute.subst(m5workbeginIop)
-
- m5workendCode = '''PseudoInst::workend(
- xc->tcBase(),
- join32to64(R1, R0),
- join32to64(R3, R2)
- );'''
-
- m5workendCode64 = '''PseudoInst::workend(
- xc->tcBase(),
- X0,
- X1
- );'''
-
- m5workendIop = InstObjParams("m5workend", "M5workend", "PredOp",
- { "code": m5workendCode,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(m5workendIop)
- decoder_output += BasicConstructor.subst(m5workendIop)
- exec_output += PredOpExecute.subst(m5workendIop)
-
- m5workendIop = InstObjParams("m5workend", "M5workend64", "PredOp",
- { "code": m5workendCode64,
- "predicate_test": predicateTest },
- ["IsNonSpeculative"])
- header_output += BasicDeclare.subst(m5workendIop)
- decoder_output += BasicConstructor.subst(m5workendIop)
- exec_output += PredOpExecute.subst(m5workendIop)
+ gem5OpIop = InstObjParams("gem5op", "Gem5Op", "PredOp",
+ { "code": gem5OpCode + \
+ 'R0 = bits(ret, 31, 0);\n' + \
+ 'R1 = bits(ret, 63, 32);',
+ "predicate_test": predicateTest },
+ [ "IsNonSpeculative", "IsUnverifiable" ]);
+ header_output += BasicDeclare.subst(gem5OpIop)
+ decoder_output += BasicConstructor.subst(gem5OpIop)
+ exec_output += PredOpExecute.subst(gem5OpIop)
}};
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27791
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https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6cb94b3d115f50d681ca855f80f9d7d3df6bc470
Gerrit-Change-Number: 27791
Gerrit-PatchSet: 28
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Earl Ou <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Gem5 Cloud Project GCB service account
<[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Yu-hsin Wang <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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