Boris Shingarov has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37295 )
Change subject: arch-power: Implement mcrxr
......................................................................
arch-power: Implement mcrxr
Implement the mcrxr instruction (Move to Condition Register from XER
X-form) as defined on p.132 of the green-cloth book:
The contents of XER<0:3> are copied into the Condition Register field
designated by BF. XER<0:3> are set to zero.
Change-Id: I82ae3d98e1eaf9182e90c0c86afe0f13d4a052e4
---
M src/arch/power/isa/decoder.isa
M src/arch/power/miscregs.hh
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 475ddcc..8e7e500 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -278,6 +278,12 @@
0x100: mtlr({{ LR = Rs; }});
0x120: mtctr({{ CTR = Rs; }});
}
+ 512: mcrxr({{
+ Xer xer = XER;
+ CR = insertCRField(CR, BF, xer.topNibble);
+ xer.topNibble = 0;
+ XER = xer;
+ }});
}
// All loads with an index register. The non-update versions
diff --git a/src/arch/power/miscregs.hh b/src/arch/power/miscregs.hh
index f7d9e3b..e220888 100644
--- a/src/arch/power/miscregs.hh
+++ b/src/arch/power/miscregs.hh
@@ -55,6 +55,7 @@
Bitfield<31> so;
Bitfield<30> ov;
Bitfield<29> ca;
+ Bitfield<31, 28> topNibble;
EndBitUnion(Xer)
BitUnion32(Fpscr)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I82ae3d98e1eaf9182e90c0c86afe0f13d4a052e4
Gerrit-Change-Number: 37295
Gerrit-PatchSet: 1
Gerrit-Owner: Boris Shingarov <shinga...@gmail.com>
Gerrit-MessageType: newchange
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