Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34979 )
Change subject: arch-x86: Replace any getDTBPtr/getITBPtr usage
......................................................................
arch-x86: Replace any getDTBPtr/getITBPtr usage
The getMMUPtr should be used instead
JIRA: https://gem5.atlassian.net/browse/GEM5-790
Change-Id: I363c2b50abdd5d2d8442ebf5892eaf17c99c129a
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34979
Maintainer: Gabe Black <[email protected]>
Tested-by: kokoro <[email protected]>
Reviewed-by: Jason Lowe-Power <[email protected]>
---
M src/arch/x86/faults.cc
M src/arch/x86/isa.cc
M src/arch/x86/mmu.hh
M src/arch/x86/remote_gdb.cc
M src/arch/x86/utility.cc
5 files changed, 25 insertions(+), 13 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index 36cc47e..a507515 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -42,6 +42,7 @@
#include "arch/x86/generated/decoder.hh"
#include "arch/x86/isa_traits.hh"
+#include "arch/x86/mmu.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
@@ -137,8 +138,7 @@
{
if (FullSystem) {
// Invalidate any matching TLB entries before handling the page
fault.
- tc->getITBPtr()->demapPage(addr, 0);
- tc->getDTBPtr()->demapPage(addr, 0);
+ tc->getMMUPtr()->demapPage(addr, 0);
HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
X86FaultBase::invoke(tc);
// If something bad happens while trying to enter the page fault
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 1b2504a..8618287 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -29,7 +29,7 @@
#include "arch/x86/isa.hh"
#include "arch/x86/decoder.hh"
-#include "arch/x86/tlb.hh"
+#include "arch/x86/mmu.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "params/X86ISA.hh"
@@ -239,8 +239,7 @@
}
}
if (toggled.pg) {
- dynamic_cast<TLB *>(tc->getITBPtr())->flushAll();
- dynamic_cast<TLB *>(tc->getDTBPtr())->flushAll();
+ tc->getMMUPtr()->flushAll();
}
//This must always be 1.
newCR0.et = 1;
@@ -255,15 +254,13 @@
case MISCREG_CR2:
break;
case MISCREG_CR3:
- dynamic_cast<TLB *>(tc->getITBPtr())->flushNonGlobal();
- dynamic_cast<TLB *>(tc->getDTBPtr())->flushNonGlobal();
+ static_cast<MMU *>(tc->getMMUPtr())->flushNonGlobal();
break;
case MISCREG_CR4:
{
CR4 toggled = regVal[miscReg] ^ val;
if (toggled.pae || toggled.pse || toggled.pge) {
- dynamic_cast<TLB *>(tc->getITBPtr())->flushAll();
- dynamic_cast<TLB *>(tc->getDTBPtr())->flushAll();
+ tc->getMMUPtr()->flushAll();
}
}
break;
diff --git a/src/arch/x86/mmu.hh b/src/arch/x86/mmu.hh
index 4f3411a..70afea3 100644
--- a/src/arch/x86/mmu.hh
+++ b/src/arch/x86/mmu.hh
@@ -39,6 +39,7 @@
#define __ARCH_X86_MMU_HH__
#include "arch/generic/mmu.hh"
+#include "arch/x86/tlb.hh"
#include "params/X86MMU.hh"
@@ -50,6 +51,19 @@
MMU(const X86MMUParams &p)
: BaseMMU(p)
{}
+
+ void
+ flushNonGlobal()
+ {
+ static_cast<TLB*>(itb)->flushNonGlobal();
+ static_cast<TLB*>(dtb)->flushNonGlobal();
+ }
+
+ Walker*
+ getDataWalker()
+ {
+ return static_cast<TLB*>(dtb)->getWalker();
+ }
};
} // namespace X86ISA
diff --git a/src/arch/x86/remote_gdb.cc b/src/arch/x86/remote_gdb.cc
index 9603b90..2f38fd5f 100644
--- a/src/arch/x86/remote_gdb.cc
+++ b/src/arch/x86/remote_gdb.cc
@@ -44,6 +44,7 @@
#include <string>
+#include "arch/x86/mmu.hh"
#include "arch/x86/pagetable_walker.hh"
#include "arch/x86/process.hh"
#include "arch/x86/regs/int.hh"
@@ -68,8 +69,8 @@
RemoteGDB::acc(Addr va, size_t len)
{
if (FullSystem) {
- Walker *walker = dynamic_cast<TLB *>(
- context()->getDTBPtr())->getWalker();
+ Walker *walker = dynamic_cast<MMU *>(
+ context()->getMMUPtr())->getDataWalker();
unsigned logBytes;
Fault fault = walker->startFunctional(context(), va, logBytes,
BaseTLB::Read);
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 33b9371..7d891af 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -39,6 +39,7 @@
#include "arch/x86/utility.hh"
#include "arch/x86/interrupts.hh"
+#include "arch/x86/mmu.hh"
#include "arch/x86/registers.hh"
#include "arch/x86/x86_traits.hh"
#include "cpu/base.hh"
@@ -86,8 +87,7 @@
// CPU switch have different frequencies.
dest->setMiscReg(MISCREG_TSC, src->readMiscReg(MISCREG_TSC));
- dest->getITBPtr()->flushAll();
- dest->getDTBPtr()->flushAll();
+ dest->getMMUPtr()->flushAll();
}
void
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34979
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I363c2b50abdd5d2d8442ebf5892eaf17c99c129a
Gerrit-Change-Number: 34979
Gerrit-PatchSet: 17
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Anthony Gutierrez <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Matthew Poremba <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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