Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34980 )
Change subject: arch-riscv: Replace any getDTBPtr/getITBPtr usage
......................................................................
arch-riscv: Replace any getDTBPtr/getITBPtr usage
The getMMUPtr should be used instead
JIRA: https://gem5.atlassian.net/browse/GEM5-790
Change-Id: I46282b43b53b7dc9f9c6bb959d4aa23ee6808a6b
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34980
Reviewed-by: Jason Lowe-Power <[email protected]>
Maintainer: Jason Lowe-Power <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/includes.isa
M src/arch/riscv/mmu.hh
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/tlb.cc
5 files changed, 25 insertions(+), 10 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index b39005f..5ef68fe 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1848,8 +1848,7 @@
"sfence in user mode or TVM
enabled",
machInst);
}
- xc->tcBase()->getITBPtr()->demapPage(Rs1, Rs2);
- xc->tcBase()->getDTBPtr()->demapPage(Rs1, Rs2);
+ xc->tcBase()->getMMUPtr()->demapPage(Rs1, Rs2);
}}, IsNonSpeculative, IsSerializeAfter, No_OpClass);
0x18: mret({{
if (xc->readMiscReg(MISCREG_PRV) != PRV_M) {
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index 16114c9..009f143 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -61,7 +61,7 @@
#include "arch/riscv/decoder.hh"
#include "arch/riscv/faults.hh"
-#include "arch/riscv/tlb.hh"
+#include "arch/riscv/mmu.hh"
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
@@ -81,6 +81,7 @@
#include "arch/generic/memhelpers.hh"
#include "arch/riscv/faults.hh"
+#include "arch/riscv/mmu.hh"
#include "arch/riscv/registers.hh"
#include "arch/riscv/utility.hh"
#include "base/condcodes.hh"
diff --git a/src/arch/riscv/mmu.hh b/src/arch/riscv/mmu.hh
index d10ce13..322f0af 100644
--- a/src/arch/riscv/mmu.hh
+++ b/src/arch/riscv/mmu.hh
@@ -39,6 +39,8 @@
#define __ARCH_RISCV_MMU_HH__
#include "arch/generic/mmu.hh"
+#include "arch/riscv/isa.hh"
+#include "arch/riscv/tlb.hh"
#include "params/RiscvMMU.hh"
@@ -50,6 +52,18 @@
MMU(const RiscvMMUParams &p)
: BaseMMU(p)
{}
+
+ PrivilegeMode
+ getMemPriv(ThreadContext *tc, BaseTLB::Mode mode)
+ {
+ return static_cast<TLB*>(dtb)->getMemPriv(tc, mode);
+ }
+
+ Walker *
+ getDataWalker()
+ {
+ return static_cast<TLB*>(dtb)->getWalker();
+ }
};
} // namespace RiscvISA
diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index 7da666d..0e4c544 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -134,9 +134,9 @@
#include <string>
+#include "arch/riscv/mmu.hh"
#include "arch/riscv/pagetable_walker.hh"
#include "arch/riscv/registers.hh"
-#include "arch/riscv/tlb.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "mem/page_table.hh"
@@ -155,15 +155,15 @@
{
if (FullSystem)
{
- TLB *tlb = dynamic_cast<TLB *>(context()->getDTBPtr());
+ MMU *mmu = static_cast<MMU *>(context()->getMMUPtr());
unsigned logBytes;
Addr paddr = va;
- PrivilegeMode pmode = tlb->getMemPriv(context(), BaseTLB::Read);
+ PrivilegeMode pmode = mmu->getMemPriv(context(), BaseTLB::Read);
SATP satp = context()->readMiscReg(MISCREG_SATP);
if (pmode != PrivilegeMode::PRV_M &&
satp.mode != AddrXlateMode::BARE) {
- Walker *walker = tlb->getWalker();
+ Walker *walker = mmu->getDataWalker();
Fault fault = walker->startFunctional(
context(), paddr, logBytes, BaseTLB::Read);
if (fault != NoFault)
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 883a6ca..62517e9 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -35,6 +35,7 @@
#include "arch/riscv/faults.hh"
#include "arch/riscv/fs_workload.hh"
+#include "arch/riscv/mmu.hh"
#include "arch/riscv/pagetable.hh"
#include "arch/riscv/pagetable_walker.hh"
#include "arch/riscv/pra_constants.hh"
@@ -411,13 +412,13 @@
Addr paddr = vaddr;
if (FullSystem) {
- TLB *tlb = dynamic_cast<TLB *>(tc->getDTBPtr());
+ MMU *mmu = static_cast<MMU *>(tc->getMMUPtr());
- PrivilegeMode pmode = tlb->getMemPriv(tc, mode);
+ PrivilegeMode pmode = mmu->getMemPriv(tc, mode);
SATP satp = tc->readMiscReg(MISCREG_SATP);
if (pmode != PrivilegeMode::PRV_M &&
satp.mode != AddrXlateMode::BARE) {
- Walker *walker = tlb->getWalker();
+ Walker *walker = mmu->getDataWalker();
unsigned logBytes;
Fault fault = walker->startFunctional(
tc, paddr, logBytes, mode);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34980
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I46282b43b53b7dc9f9c6bb959d4aa23ee6808a6b
Gerrit-Change-Number: 34980
Gerrit-PatchSet: 17
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-CC: Gabe Black <[email protected]>
Gerrit-MessageType: merged
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