Hello Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/34975
to review the following change.
Change subject: arch: Add generic BaseMMU
......................................................................
arch: Add generic BaseMMU
This is an abstract class encapsulating the ITB and DTB
(Instruction and Data TLBs)
Change-Id: I7c8fa2ada319e631564182075da1aaff517ec212
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/arch/arm/ArmTLB.py
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/generic/BaseTLB.py
M src/arch/generic/tlb.hh
M src/arch/mips/MipsTLB.py
M src/arch/mips/tlb.cc
M src/arch/mips/tlb.hh
M src/arch/power/PowerTLB.py
M src/arch/power/tlb.cc
M src/arch/power/tlb.hh
M src/arch/riscv/RiscvTLB.py
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
M src/arch/sparc/SparcTLB.py
M src/arch/sparc/tlb.cc
M src/arch/sparc/tlb.hh
M src/arch/x86/X86TLB.py
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
20 files changed, 195 insertions(+), 7 deletions(-)
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index a821a04..69ac73a 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -38,7 +38,7 @@
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
-from m5.objects.BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB, BaseMMU
from m5.objects.ClockedObject import ClockedObject
# Basic stage 1 translation objects
@@ -102,3 +102,10 @@
class ArmDTB(ArmTLB):
stage2_mmu = ArmStage2DMMU()
+
+class ArmMMU(BaseMMU):
+ type = 'ArmMMU'
+ cxx_class = 'ArmISA::MMU'
+ cxx_header = 'arch/arm/tlb.hh'
+ itb = ArmITB()
+ dtb = ArmDTB()
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 413a13e..0010774 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -64,6 +64,7 @@
#include "mem/packet_access.hh"
#include "mem/page_table.hh"
#include "mem/request.hh"
+#include "params/ArmMMU.hh"
#include "params/ArmTLB.hh"
#include "sim/full_system.hh"
#include "sim/process.hh"
@@ -1638,9 +1639,18 @@
}
}
+MMU::MMU(const ArmMMUParams *p)
+ : BaseMMU(p)
+{}
ArmISA::TLB *
ArmTLBParams::create()
{
return new ArmISA::TLB(this);
}
+
+ArmISA::MMU *
+ArmMMUParams::create()
+{
+ return new ArmISA::MMU(this);
+}
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 63928cb..ac9c383 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -49,6 +49,7 @@
#include "arch/generic/tlb.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
+#include "params/ArmMMU.hh"
#include "params/ArmTLB.hh"
#include "sim/probe/pmu.hh"
@@ -465,6 +466,12 @@
LookupLevel lookup_level);
};
+class MMU : public BaseMMU
+{
+ public:
+ MMU(const ArmMMUParams *p);
+};
+
template<typename T>
TLB *
getITBPtr(T *tc)
diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py
index 03fb68b..207e4ae 100644
--- a/src/arch/generic/BaseTLB.py
+++ b/src/arch/generic/BaseTLB.py
@@ -39,3 +39,10 @@
mem_side_port = RequestPort("Port closer to memory side")
master = DeprecatedParam(mem_side_port,
'`master` is now called `mem_side_port`')
+
+class BaseMMU(SimObject):
+ type = 'BaseMMU'
+ abstract = True
+ cxx_header = "arch/generic/tlb.hh"
+ itb = Param.BaseTLB("Instruction TLB")
+ dtb = Param.BaseTLB("Data TLB")
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index f144f69..59e9f3b 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -43,6 +43,7 @@
#include "base/logging.hh"
#include "mem/request.hh"
+#include "params/BaseMMU.hh"
#include "sim/sim_object.hh"
class ThreadContext;
@@ -139,4 +140,40 @@
void memInvalidate() { flushAll(); }
};
+class BaseMMU : public SimObject
+{
+ protected:
+ typedef BaseMMUParams Params;
+
+ BaseMMU(const Params *p)
+ : SimObject(p), dtb(p->dtb), itb(p->itb)
+ {}
+
+ public:
+ enum TLBType
+ {
+ I_TLBS = 0x01,
+ D_TLBS = 0x10,
+ ALL_TLBS = 0x11
+ };
+
+ void
+ flushAll()
+ {
+ dtb->flushAll();
+ itb->flushAll();
+ }
+
+ void
+ demapPage(Addr vaddr, uint64_t asn)
+ {
+ itb->demapPage(vaddr, asn);
+ dtb->demapPage(vaddr, asn);
+ }
+
+ public:
+ BaseTLB* dtb;
+ BaseTLB* itb;
+};
+
#endif // __ARCH_GENERIC_TLB_HH__
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index d43b6d7..9a8a07d 100644
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -29,10 +29,17 @@
from m5.SimObject import SimObject
from m5.params import *
-from m5.objects.BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB, BaseMMU
class MipsTLB(BaseTLB):
type = 'MipsTLB'
cxx_class = 'MipsISA::TLB'
cxx_header = 'arch/mips/tlb.hh'
size = Param.Int(64, "TLB size")
+
+class MipsMMU(BaseMMU):
+ type = 'MipsMMU'
+ cxx_class = 'MipsISA::MMU'
+ cxx_header = 'arch/mips/tlb.hh'
+ itb = MipsTLB()
+ dtb = MipsTLB()
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 49092ef..3582930 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -258,8 +258,18 @@
return *pte;
}
+MMU::MMU(const MipsMMUParams *p)
+ : BaseMMU(p)
+{}
+
MipsISA::TLB *
MipsTLBParams::create()
{
- return new TLB(this);
+ return new MipsISA::TLB(this);
+}
+
+MipsISA::MMU *
+MipsMMUParams::create()
+{
+ return new MipsISA::MMU(this);
}
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 2be2ddf..47aa3b1 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -38,6 +38,7 @@
#include "arch/mips/utility.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
+#include "params/MipsMMU.hh"
#include "params/MipsTLB.hh"
#include "sim/sim_object.hh"
@@ -104,6 +105,12 @@
ThreadContext *tc, Mode mode) const override;
};
+class MMU : public BaseMMU
+{
+ public:
+ MMU(const MipsMMUParams *p);
+};
+
}
diff --git a/src/arch/power/PowerTLB.py b/src/arch/power/PowerTLB.py
index 7f9a271..c368ce3 100644
--- a/src/arch/power/PowerTLB.py
+++ b/src/arch/power/PowerTLB.py
@@ -29,10 +29,17 @@
from m5.SimObject import SimObject
from m5.params import *
-from m5.objects.BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB, BaseMMU
class PowerTLB(BaseTLB):
type = 'PowerTLB'
cxx_class = 'PowerISA::TLB'
cxx_header = 'arch/power/tlb.hh'
size = Param.Int(64, "TLB size")
+
+class PowerMMU(BaseMMU):
+ type = 'PowerMMU'
+ cxx_class = 'PowerISA::MMU'
+ cxx_header = 'arch/power/tlb.hh'
+ itb = PowerTLB()
+ dtb = PowerTLB()
diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc
index 2726ca3..58caf5a 100644
--- a/src/arch/power/tlb.cc
+++ b/src/arch/power/tlb.cc
@@ -280,8 +280,18 @@
return *pte;
}
+MMU::MMU(const PowerMMUParams *p)
+ : BaseMMU(p)
+{}
+
PowerISA::TLB *
PowerTLBParams::create()
{
return new PowerISA::TLB(this);
}
+
+PowerISA::MMU *
+PowerMMUParams::create()
+{
+ return new PowerISA::MMU(this);
+}
diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh
index c119d93..e3a6dd6 100644
--- a/src/arch/power/tlb.hh
+++ b/src/arch/power/tlb.hh
@@ -40,6 +40,7 @@
#include "arch/power/utility.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
+#include "params/PowerMMU.hh"
#include "params/PowerTLB.hh"
class ThreadContext;
@@ -160,6 +161,12 @@
void unserialize(CheckpointIn &cp) override;
};
+class MMU : public BaseMMU
+{
+ public:
+ MMU(const PowerMMUParams *p);
+};
+
} // namespace PowerISA
#endif // __ARCH_POWER_TLB_HH__
diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py
index 4844feb..6a68f3a 100644
--- a/src/arch/riscv/RiscvTLB.py
+++ b/src/arch/riscv/RiscvTLB.py
@@ -30,7 +30,7 @@
from m5.params import *
from m5.proxy import *
-from m5.objects.BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB, BaseMMU
from m5.objects.ClockedObject import ClockedObject
class RiscvPagetableWalker(ClockedObject):
@@ -49,3 +49,10 @@
size = Param.Int(64, "TLB size")
walker = Param.RiscvPagetableWalker(\
RiscvPagetableWalker(), "page table walker")
+
+class RiscvMMU(BaseMMU):
+ type = 'RiscvMMU'
+ cxx_class = 'RiscvISA::MMU'
+ cxx_header = 'arch/riscv/tlb.hh'
+ itb = RiscvTLB()
+ dtb = RiscvTLB()
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 34ccc03..caa2a7a 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -512,8 +512,18 @@
{
}
+MMU::MMU(const RiscvMMUParams *p)
+ : BaseMMU(p)
+{}
+
RiscvISA::TLB *
RiscvTLBParams::create()
{
return new TLB(this);
}
+
+RiscvISA::MMU *
+RiscvMMUParams::create()
+{
+ return new RiscvISA::MMU(this);
+}
diff --git a/src/arch/riscv/tlb.hh b/src/arch/riscv/tlb.hh
index a92bdd2..9604b53 100644
--- a/src/arch/riscv/tlb.hh
+++ b/src/arch/riscv/tlb.hh
@@ -40,6 +40,7 @@
#include "arch/riscv/utility.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
+#include "params/RiscvMMU.hh"
#include "params/RiscvTLB.hh"
#include "sim/sim_object.hh"
@@ -128,6 +129,12 @@
Translation *translation, Mode mode, bool &delayed);
};
+class MMU : public BaseMMU
+{
+ public:
+ MMU(const RiscvMMUParams *p);
+};
+
}
#endif // __RISCV_MEMORY_HH__
diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py
index 6878bef..e60e73f 100644
--- a/src/arch/sparc/SparcTLB.py
+++ b/src/arch/sparc/SparcTLB.py
@@ -27,10 +27,17 @@
from m5.SimObject import SimObject
from m5.params import *
-from m5.objects.BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB, BaseMMU
class SparcTLB(BaseTLB):
type = 'SparcTLB'
cxx_class = 'SparcISA::TLB'
cxx_header = 'arch/sparc/tlb.hh'
size = Param.Int(64, "TLB size")
+
+class SparcMMU(BaseMMU):
+ type = 'SparcMMU'
+ cxx_class = 'SparcISA::MMU'
+ cxx_header = 'arch/sparc/tlb.hh'
+ itb = SparcTLB()
+ dtb = SparcTLB()
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index fcb0973..2a8fdb9 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -1505,6 +1505,10 @@
UNSERIALIZE_SCALAR(sfar);
}
+MMU::MMU(const SparcMMUParams *p)
+ : BaseMMU(p)
+{}
+
} // namespace SparcISA
SparcISA::TLB *
@@ -1512,3 +1516,9 @@
{
return new SparcISA::TLB(this);
}
+
+SparcISA::MMU *
+SparcMMUParams::create()
+{
+ return new SparcISA::MMU(this);
+}
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 15333ab..bdda832 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -34,6 +34,7 @@
#include "arch/sparc/tlb_map.hh"
#include "base/logging.hh"
#include "mem/request.hh"
+#include "params/SparcMMU.hh"
#include "params/SparcTLB.hh"
class ThreadContext;
@@ -199,6 +200,12 @@
ASI cacheAsi[2];
};
+class MMU : public BaseMMU
+{
+ public:
+ MMU(const SparcMMUParams *p);
+};
+
}
#endif // __ARCH_SPARC_TLB_HH__
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index d9dd980..a9fdfa9 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -36,7 +36,7 @@
from m5.params import *
from m5.proxy import *
-from m5.objects.BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB, BaseMMU
from m5.objects.ClockedObject import ClockedObject
class X86PagetableWalker(ClockedObject):
@@ -56,3 +56,10 @@
system = Param.System(Parent.any, "system object")
walker = Param.X86PagetableWalker(\
X86PagetableWalker(), "page table walker")
+
+class X86MMU(BaseMMU):
+ type = 'X86MMU'
+ cxx_class = 'X86ISA::MMU'
+ cxx_header = 'arch/x86/tlb.hh'
+ itb = X86TLB()
+ dtb = X86TLB()
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 11ce660..29e1e20 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -570,6 +570,10 @@
return &walker->getPort("port");
}
+MMU::MMU(const X86MMUParams *p)
+ : BaseMMU(p)
+{}
+
} // namespace X86ISA
X86ISA::TLB *
@@ -577,3 +581,9 @@
{
return new X86ISA::TLB(this);
}
+
+X86ISA::MMU *
+X86MMUParams::create()
+{
+ return new X86ISA::MMU(this);
+}
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 671b165..4cf2eb4 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -45,6 +45,7 @@
#include "arch/x86/pagetable.hh"
#include "base/trie.hh"
#include "mem/request.hh"
+#include "params/X86MMU.hh"
#include "params/X86TLB.hh"
#include "sim/stats.hh"
@@ -168,6 +169,12 @@
*/
Port *getTableWalkerPort() override;
};
+
+ class MMU : public BaseMMU
+ {
+ public:
+ MMU(const X86MMUParams *p);
+ };
}
#endif // __ARCH_X86_TLB_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34975
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7c8fa2ada319e631564182075da1aaff517ec212
Gerrit-Change-Number: 34975
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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