Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34876 )
Change subject: arch-arm: Add ID_MMFR4{,EL1} system registers
......................................................................
arch-arm: Add ID_MMFR4{,EL1} system registers
Change-Id: Id50ebd2ef2e69ecbd3b7f64a4e9eafe00e283806
---
M src/arch/arm/ArmISA.py
M src/arch/arm/insts/misc64.cc
M src/arch/arm/isa.cc
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/utility.cc
7 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index ebad774..ef6b1a0 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -71,6 +71,7 @@
# SuperSec | Coherent TLB | Bcast Maint |
# BP Maint | Cache Maint Set/way | Cache Maint MVA
id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3")
+ id_mmfr4 = Param.UInt32(0x00000000, "Memory Model Feature Register 4")
# See section B4.1.84 of ARM ARM
# All values are latest for ARMv7-A profile
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 47a8ad9..e0b5189 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -365,7 +365,7 @@
case MISCREG_ID_MMFR1_EL1:
case MISCREG_ID_MMFR2_EL1:
case MISCREG_ID_MMFR3_EL1:
- //case MISCREG_ID_MMFR4_EL1:
+ case MISCREG_ID_MMFR4_EL1:
case MISCREG_ID_ISAR0_EL1:
case MISCREG_ID_ISAR1_EL1:
case MISCREG_ID_ISAR2_EL1:
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9ace236..1b6ed72 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -349,6 +349,7 @@
miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
+ miscRegs[MISCREG_ID_MMFR4] = p->id_mmfr4;
miscRegs[MISCREG_ID_ISAR5] = insertBits(
miscRegs[MISCREG_ID_ISAR5], 19, 4,
@@ -1387,6 +1388,7 @@
case MISCREG_ID_MMFR1:
case MISCREG_ID_MMFR2:
case MISCREG_ID_MMFR3:
+ case MISCREG_ID_MMFR4:
case MISCREG_ID_ISAR0:
case MISCREG_ID_ISAR1:
case MISCREG_ID_ISAR2:
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 932abc3..2a9df19 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -394,6 +394,7 @@
case 5:
return MISCREG_ID_ISAR5;
case 6:
+ return MISCREG_ID_MMFR4;
case 7:
return MISCREG_RAZ; // read as zero
}
@@ -2059,6 +2060,8 @@
return MISCREG_ID_ISAR4_EL1;
case 5:
return MISCREG_ID_ISAR5_EL1;
+ case 6:
+ return MISCREG_ID_MMFR4_EL1;
}
break;
case 3:
@@ -3767,6 +3770,8 @@
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_MMFR3)
.allPrivileges().exceptUserMode().writes(0);
+ InitReg(MISCREG_ID_MMFR4)
+ .allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_ISAR0)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_ISAR1)
@@ -4690,6 +4695,9 @@
InitReg(MISCREG_ID_MMFR3_EL1)
.allPrivileges().exceptUserMode().writes(0)
.mapsTo(MISCREG_ID_MMFR3);
+ InitReg(MISCREG_ID_MMFR4_EL1)
+ .allPrivileges().exceptUserMode().writes(0)
+ .mapsTo(MISCREG_ID_MMFR4);
InitReg(MISCREG_ID_ISAR0_EL1)
.allPrivileges().exceptUserMode().writes(0)
.mapsTo(MISCREG_ID_ISAR0);
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index f683297..964788b 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -212,6 +212,7 @@
MISCREG_ID_MMFR1,
MISCREG_ID_MMFR2,
MISCREG_ID_MMFR3,
+ MISCREG_ID_MMFR4,
MISCREG_ID_ISAR0,
MISCREG_ID_ISAR1,
MISCREG_ID_ISAR2,
@@ -541,6 +542,7 @@
MISCREG_ID_MMFR1_EL1,
MISCREG_ID_MMFR2_EL1,
MISCREG_ID_MMFR3_EL1,
+ MISCREG_ID_MMFR4_EL1,
MISCREG_ID_ISAR0_EL1,
MISCREG_ID_ISAR1_EL1,
MISCREG_ID_ISAR2_EL1,
@@ -1315,6 +1317,7 @@
"id_mmfr1",
"id_mmfr2",
"id_mmfr3",
+ "id_mmfr4",
"id_isar0",
"id_isar1",
"id_isar2",
@@ -1642,6 +1645,7 @@
"id_mmfr1_el1",
"id_mmfr2_el1",
"id_mmfr3_el1",
+ "id_mmfr4_el1",
"id_isar0_el1",
"id_isar1_el1",
"id_isar2_el1",
diff --git a/src/arch/arm/tracers/tarmac_parser.cc
b/src/arch/arm/tracers/tarmac_parser.cc
index c7bf977..9a21f87 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -200,6 +200,7 @@
{ "id_mmfr1", MISCREG_ID_MMFR1 },
{ "id_mmfr2", MISCREG_ID_MMFR2 },
{ "id_mmfr3", MISCREG_ID_MMFR3 },
+ { "id_mmfr4", MISCREG_ID_MMFR4 },
{ "id_isar0", MISCREG_ID_ISAR0 },
{ "id_isar1", MISCREG_ID_ISAR1 },
{ "id_isar2", MISCREG_ID_ISAR2 },
@@ -498,6 +499,7 @@
{ "id_mmfr1_el1", MISCREG_ID_MMFR1_EL1 },
{ "id_mmfr2_el1", MISCREG_ID_MMFR2_EL1 },
{ "id_mmfr3_el1", MISCREG_ID_MMFR3_EL1 },
+ { "id_mmfr4_el1", MISCREG_ID_MMFR4_EL1 },
{ "id_isar0_el1", MISCREG_ID_ISAR0_EL1 },
{ "id_isar1_el1", MISCREG_ID_ISAR1_EL1 },
{ "id_isar2_el1", MISCREG_ID_ISAR2_EL1 },
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index a189c4a..cee4268 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -656,6 +656,7 @@
case MISCREG_ID_MMFR1:
case MISCREG_ID_MMFR2:
case MISCREG_ID_MMFR3:
+ case MISCREG_ID_MMFR4:
case MISCREG_ID_ISAR0:
case MISCREG_ID_ISAR1:
case MISCREG_ID_ISAR2:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id50ebd2ef2e69ecbd3b7f64a4e9eafe00e283806
Gerrit-Change-Number: 34876
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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