[gem5-dev] Change in gem5/gem5[develop]: mips,cpu: Get rid of the IsCondDelaySlot StaticInst flag.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33736 )

Change subject: mips,cpu: Get rid of the IsCondDelaySlot StaticInst flag.
......................................................................

mips,cpu: Get rid of the IsCondDelaySlot StaticInst flag.

This is set by MIPS in a few places, but not actually used by anything.

Change-Id: Iaf3b29b2c14bb1de3ffd6a0035f12f238591cb60
---
M src/arch/mips/isa/formats/branch.isa
M src/cpu/StaticInstFlags.py
M src/cpu/base_dyn_inst.hh
M src/cpu/static_inst.hh
4 files changed, 0 insertions(+), 6 deletions(-)



diff --git a/src/arch/mips/isa/formats/branch.isa  
b/src/arch/mips/isa/formats/branch.isa
index 4975a13..7c2b27c 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -241,7 +241,6 @@
             code += 'R31 = NNPC;\n'
         elif x == 'Likely':
             not_taken_code = 'NNPC = NPC; NPC = PC;'
-            inst_flags += ('IsCondDelaySlot', )
         else:
             inst_flags += (x, )

@@ -280,7 +279,6 @@
             code += 'R32 = NNPC;'
         elif x == 'Likely':
             not_taken_code = 'NNPC = NPC, NPC = PC;'
-            inst_flags += ('IsCondDelaySlot', )
         else:
             inst_flags += (x, )

diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py
index 7e3d4ef..f387dfd 100644
--- a/src/cpu/StaticInstFlags.py
+++ b/src/cpu/StaticInstFlags.py
@@ -75,8 +75,6 @@
         'IsCall',           # Subroutine call.
         'IsReturn',         # Subroutine return.

-        'IsCondDelaySlot',  # Conditional Delay-Slot Instruction
-
         'IsThreadSync',     # Thread synchronization operation.

         'IsSerializing',    # Serializes pipeline: won't execute until all
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index b98cbaa..b2cf5a6 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -517,7 +517,6 @@
     bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
     bool isCondCtrl()     const { return staticInst->isCondCtrl(); }
     bool isUncondCtrl()   const { return staticInst->isUncondCtrl(); }
-    bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
     bool isThreadSync()   const { return staticInst->isThreadSync(); }
     bool isSerializing()  const { return staticInst->isSerializing(); }
     bool isSerializeBefore() const
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index b523ef9..619c3b5 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -179,7 +179,6 @@
     bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
     bool isCondCtrl()     const { return flags[IsCondControl]; }
     bool isUncondCtrl()   const { return flags[IsUncondControl]; }
-    bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }

     bool isThreadSync()   const { return flags[IsThreadSync]; }
     bool isSerializing()  const { return flags[IsSerializing] ||

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iaf3b29b2c14bb1de3ffd6a0035f12f238591cb60
Gerrit-Change-Number: 33736
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabebl...@google.com>
Gerrit-MessageType: newchange
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