Shivani Parekh has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33639 )
Change subject: dev-arm: Update functions in smmu files
......................................................................
dev-arm: Update functions in smmu files
masterTableWalkRecvTimingResp(), atsSlaveRecvAtomic() scheduleSlaveRetries()
Change-Id: I9c7116a6be0dc2137f043cd7811a803a77d78aee
---
M src/dev/arm/smmu_v3.cc
M src/dev/arm/smmu_v3.hh
M src/dev/arm/smmu_v3_ports.cc
M src/dev/arm/smmu_v3_slaveifc.cc
M src/dev/arm/smmu_v3_slaveifc.hh
M src/dev/arm/smmu_v3_transl.cc
6 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/src/dev/arm/smmu_v3.cc b/src/dev/arm/smmu_v3.cc
index 004cb68..8e3dddf 100644
--- a/src/dev/arm/smmu_v3.cc
+++ b/src/dev/arm/smmu_v3.cc
@@ -124,7 +124,7 @@
}
bool
-SMMUv3::masterRecvTimingResp(PacketPtr pkt)
+SMMUv3::requestorRecvTimingResp(PacketPtr pkt)
{
DPRINTF(SMMUv3, "[t] master resp addr=%#x size=%#x\n",
pkt->getAddr(), pkt->getSize());
@@ -141,7 +141,7 @@
}
void
-SMMUv3::masterRecvReqRetry()
+SMMUv3::requestorRecvReqRetry()
{
assert(!packetsToRetry.empty());
@@ -165,12 +165,12 @@
* If the slave port was stalled then unstall it (send retry).
*/
if (a.type == ACTION_SEND_REQ_FINAL)
- scheduleSlaveRetries();
+ scheduleResponseRetries();
}
}
bool
-SMMUv3::masterTableWalkRecvTimingResp(PacketPtr pkt)
+SMMUv3::requestTableWalkRecvTimingResp(PacketPtr pkt)
{
DPRINTF(SMMUv3, "[t] master HWTW resp addr=%#x size=%#x\n",
pkt->getAddr(), pkt->getSize());
@@ -187,7 +187,7 @@
}
void
-SMMUv3::masterTableWalkRecvReqRetry()
+SMMUv3::requestTableWalkRecvReqRetry()
{
assert(tableWalkPortEnable);
assert(!packetsTableWalkToRetry.empty());
@@ -208,7 +208,7 @@
}
void
-SMMUv3::scheduleSlaveRetries()
+SMMUv3::scheduleResponseRetries()
{
for (auto ifc : slaveInterfaces) {
ifc->scheduleDeviceRetry();
@@ -294,7 +294,7 @@
if (packetsTableWalkToRetry.empty()
&& masterTableWalkPort.sendTimingReq(action.pkt)) {
- scheduleSlaveRetries();
+ scheduleResponseRetries();
} else {
DPRINTF(SMMUv3, "[t] master HWTW req needs retry,"
" qlen=%d\n", packetsTableWalkToRetry.size());
@@ -311,7 +311,7 @@
action.pkt->getAddr(), action.pkt->getSize());
if (packetsToRetry.empty() &&
masterPort.sendTimingReq(action.pkt)) {
- scheduleSlaveRetries();
+ scheduleResponseRetries();
} else {
DPRINTF(SMMUv3, "[t] master req needs retry, qlen=%d\n",
packetsToRetry.size());
diff --git a/src/dev/arm/smmu_v3.hh b/src/dev/arm/smmu_v3.hh
index 8f35cdf..0d2ea51 100644
--- a/src/dev/arm/smmu_v3.hh
+++ b/src/dev/arm/smmu_v3.hh
@@ -151,7 +151,7 @@
std::queue<SMMUAction> packetsTableWalkToRetry;
- void scheduleSlaveRetries();
+ void scheduleResponseRetries();
SMMUAction runProcess(SMMUProcess *proc, PacketPtr pkt);
SMMUAction runProcessAtomic(SMMUProcess *proc, PacketPtr pkt);
@@ -171,13 +171,13 @@
virtual void init() override;
virtual void regStats() override;
- Tick slaveRecvAtomic(PacketPtr pkt, PortID id);
- bool slaveRecvTimingReq(PacketPtr pkt, PortID id);
- bool masterRecvTimingResp(PacketPtr pkt);
- void masterRecvReqRetry();
+ Tick responderRecvAtomic(PacketPtr pkt, PortID id);
+ bool responderRecvTimingReq(PacketPtr pkt, PortID id);
+ bool requestorRecvTimingResp(PacketPtr pkt);
+ void requestorRecvReqRetry();
- bool masterTableWalkRecvTimingResp(PacketPtr pkt);
- void masterTableWalkRecvReqRetry();
+ bool requestTableWalkRecvTimingResp(PacketPtr pkt);
+ void requestTableWalkRecvReqRetry();
Tick readControl(PacketPtr pkt);
Tick writeControl(PacketPtr pkt);
diff --git a/src/dev/arm/smmu_v3_ports.cc b/src/dev/arm/smmu_v3_ports.cc
index 3f54250..0168b14 100644
--- a/src/dev/arm/smmu_v3_ports.cc
+++ b/src/dev/arm/smmu_v3_ports.cc
@@ -49,13 +49,13 @@
bool
SMMUMasterPort::recvTimingResp(PacketPtr pkt)
{
- return smmu.masterRecvTimingResp(pkt);
+ return smmu.requestorRecvTimingResp(pkt);
}
void
SMMUMasterPort::recvReqRetry()
{
- return smmu.masterRecvReqRetry();
+ return smmu.requestorRecvReqRetry();
}
SMMUMasterTableWalkPort::SMMUMasterTableWalkPort(const std::string &_name,
@@ -67,13 +67,13 @@
bool
SMMUMasterTableWalkPort::recvTimingResp(PacketPtr pkt)
{
- return smmu.masterTableWalkRecvTimingResp(pkt);
+ return smmu.requestTableWalkRecvTimingResp(pkt);
}
void
SMMUMasterTableWalkPort::recvReqRetry()
{
- return smmu.masterTableWalkRecvReqRetry();
+ return smmu.requestTableWalkRecvReqRetry();
}
SMMUSlavePort::SMMUSlavePort(const std::string &_name,
@@ -147,7 +147,7 @@
bool
SMMUATSMasterPort::recvTimingResp(PacketPtr pkt)
{
- return ifc.atsMasterRecvTimingResp(pkt);
+ return ifc.atsRequestorRecvTimingResp(pkt);
}
SMMUATSSlavePort::SMMUATSSlavePort(const std::string &_name,
@@ -166,11 +166,11 @@
Tick
SMMUATSSlavePort::recvAtomic(PacketPtr pkt)
{
- return ifc.atsSlaveRecvAtomic(pkt);
+ return ifc.atsResponderRecvAtomic(pkt);
}
bool
SMMUATSSlavePort::recvTimingReq(PacketPtr pkt)
{
- return ifc.atsSlaveRecvTimingReq(pkt);
+ return ifc.atsResponderRecvTimingReq(pkt);
}
diff --git a/src/dev/arm/smmu_v3_slaveifc.cc
b/src/dev/arm/smmu_v3_slaveifc.cc
index 5b3dd98..e35117b 100644
--- a/src/dev/arm/smmu_v3_slaveifc.cc
+++ b/src/dev/arm/smmu_v3_slaveifc.cc
@@ -167,7 +167,7 @@
}
Tick
-SMMUv3SlaveInterface::atsSlaveRecvAtomic(PacketPtr pkt)
+SMMUv3SlaveInterface::atsResponderRecvAtomic(PacketPtr pkt)
{
DPRINTF(SMMUv3, "[a] ATS slave req addr=%#x size=%#x\n",
pkt->getAddr(), pkt->getSize());
@@ -185,7 +185,7 @@
}
bool
-SMMUv3SlaveInterface::atsSlaveRecvTimingReq(PacketPtr pkt)
+SMMUv3SlaveInterface::atsResponderRecvTimingReq(PacketPtr pkt)
{
DPRINTF(SMMUv3, "[t] ATS slave req addr=%#x size=%#x\n",
pkt->getAddr(), pkt->getSize());
@@ -210,7 +210,7 @@
}
bool
-SMMUv3SlaveInterface::atsMasterRecvTimingResp(PacketPtr pkt)
+SMMUv3SlaveInterface::atsRequestorRecvTimingResp(PacketPtr pkt)
{
DPRINTF(SMMUv3, "[t] ATS master resp addr=%#x size=%#x\n",
pkt->getAddr(), pkt->getSize());
diff --git a/src/dev/arm/smmu_v3_slaveifc.hh
b/src/dev/arm/smmu_v3_slaveifc.hh
index e1f8ef2..30b26c3 100644
--- a/src/dev/arm/smmu_v3_slaveifc.hh
+++ b/src/dev/arm/smmu_v3_slaveifc.hh
@@ -98,9 +98,9 @@
bool recvTimingReq(PacketPtr pkt);
void schedTimingResp(PacketPtr pkt);
- Tick atsSlaveRecvAtomic(PacketPtr pkt);
- bool atsSlaveRecvTimingReq(PacketPtr pkt);
- bool atsMasterRecvTimingResp(PacketPtr pkt);
+ Tick atsResponderRecvAtomic(PacketPtr pkt);
+ bool atsResponderRecvTimingReq(PacketPtr pkt);
+ bool atsRequestorRecvTimingResp(PacketPtr pkt);
void schedAtsTimingResp(PacketPtr pkt);
void scheduleDeviceRetry();
diff --git a/src/dev/arm/smmu_v3_transl.cc b/src/dev/arm/smmu_v3_transl.cc
index c7b20f9..7d4b917 100644
--- a/src/dev/arm/smmu_v3_transl.cc
+++ b/src/dev/arm/smmu_v3_transl.cc
@@ -1242,7 +1242,7 @@
ifc.wrBufSlotsRemaining +=
(request.size + (ifc.portWidth-1)) / ifc.portWidth;
- smmu.scheduleSlaveRetries();
+ smmu.scheduleResponseRetries();
SMMUAction a;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33639
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9c7116a6be0dc2137f043cd7811a803a77d78aee
Gerrit-Change-Number: 33639
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh <[email protected]>
Gerrit-MessageType: newchange
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