Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33355 )
Change subject: arch-arm: Remove deadcode from AArch64 address translation
......................................................................
arch-arm: Remove deadcode from AArch64 address translation
There's no need to check for CPSR.WIDTH: if the 64 bit version
of the AT instruction/register is used, it means we are already
in AArch64 execution mode
Change-Id: I1263dcfd04e791eb390199546c177a926c71c6d5
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/arch/arm/isa.cc
1 file changed, 7 insertions(+), 16 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b42fdf1..1244d39 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2364,22 +2364,13 @@
// Set fault bit and FSR
FSR fsr = armFault->getFsr(tc);
- CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
- if (cpsr.width) { // AArch32
- newVal = ((fsr >> 9) & 1) << 11;
- // rearrange fault status
- newVal |= ((fsr >> 0) & 0x3f) << 1;
- newVal |= 0x1; // F bit
- newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
- newVal |= armFault->isStage2() ? 0x200 : 0;
- } else { // AArch64
- newVal = 1; // F bit
- newVal |= fsr << 1; // FST
- // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
- newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
- newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
- newVal |= 1 << 11; // RES1
- }
+ newVal = 1; // F bit
+ newVal |= fsr << 1; // FST
+ // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
+ newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
+ newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
+ newVal |= 1 << 11; // RES1
+
DPRINTF(MiscRegs,
"MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
val, fsr, newVal);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1263dcfd04e791eb390199546c177a926c71c6d5
Gerrit-Change-Number: 33355
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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