Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/32928 )
Change subject: dev,arm: Stop using TheISA in ARM specific files.
......................................................................
dev,arm: Stop using TheISA in ARM specific files.
These can use ArmISA since there's no ambiguity about what ISA is being
used with those files.
Change-Id: I02e8ea0ab70215679eb939adaa949400e878b1ed
---
M src/arch/arm/isa/insts/neon64.isa
M src/arch/arm/isa/templates/sve_mem.isa
M src/dev/arm/generic_timer.cc
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/arch/arm/isa/insts/neon64.isa
b/src/arch/arm/isa/insts/neon64.isa
index 5186de3..b9729a1 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -46,7 +46,7 @@
smallFloatTypes = ("uint32_t",)
zeroSveVecRegUpperPartCode = '''
- TheISA::ISA::zeroSveVecRegUpperPart(%s,
+ ArmISA::ISA::zeroSveVecRegUpperPart(%s,
ArmStaticInst::getCurSveVecLen<uint64_t>(xc->tcBase()));
'''
diff --git a/src/arch/arm/isa/templates/sve_mem.isa
b/src/arch/arm/isa/templates/sve_mem.isa
index 896b95c..b5c2dc0 100644
--- a/src/arch/arm/isa/templates/sve_mem.isa
+++ b/src/arch/arm/isa/templates/sve_mem.isa
@@ -146,7 +146,7 @@
%(op_rd)s;
%(ea_code)s;
- TheISA::VecRegContainer memData;
+ ArmISA::VecRegContainer memData;
auto memDataView = memData.as<MemElemType>();
%(rden_code)s;
@@ -203,7 +203,7 @@
%(op_decl)s;
%(op_rd)s;
- TheISA::VecRegContainer memData;
+ ArmISA::VecRegContainer memData;
auto memDataView = memData.as<MemElemType>();
if (xc->readMemAccPredicate()) {
@@ -233,7 +233,7 @@
%(op_rd)s;
%(ea_code)s;
- TheISA::VecRegContainer memData;
+ ArmISA::VecRegContainer memData;
auto memDataView = memData.as<MemElemType>();
%(wren_code)s;
@@ -270,7 +270,7 @@
%(op_rd)s;
%(ea_code)s;
- TheISA::VecRegContainer memData;
+ ArmISA::VecRegContainer memData;
auto memDataView = memData.as<MemElemType>();
%(wren_code)s;
@@ -929,7 +929,7 @@
%(op_rd)s;
%(ea_code)s;
- TheISA::VecRegContainer memData;
+ ArmISA::VecRegContainer memData;
auto memDataView = memData.as<Element>();
if (fault == NoFault) {
@@ -984,7 +984,7 @@
%(op_decl)s;
%(op_rd)s;
- TheISA::VecRegContainer memData;
+ ArmISA::VecRegContainer memData;
auto memDataView = memData.as<Element>();
memcpy(memData.raw_ptr<uint8_t>(), pkt->getPtr<uint8_t>(),
@@ -1017,7 +1017,7 @@
%(op_rd)s;
%(ea_code)s;
- TheISA::VecRegContainer memData;
+ ArmISA::VecRegContainer memData;
auto memDataView = memData.as<Element>();
%(wren_code)s;
@@ -1054,7 +1054,7 @@
%(op_rd)s;
%(ea_code)s;
- TheISA::VecRegContainer memData;
+ ArmISA::VecRegContainer memData;
auto memDataView = memData.as<Element>();
%(wren_code)s;
diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index a620eec..da8de08 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -1273,7 +1273,7 @@
void
GenericTimerMem::validateFrameRange(const AddrRange &range)
{
- fatal_if(range.start() % TheISA::PageBytes,
+ fatal_if(range.start() % ArmISA::PageBytes,
"GenericTimerMem::validateFrameRange: Architecture states
each "
"register frame should be in a separate memory page,
specified "
"range base address [0x%x] is not compliant\n");
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I02e8ea0ab70215679eb939adaa949400e878b1ed
Gerrit-Change-Number: 32928
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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