Kyle Roarty has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/32234 )
Change subject: arch-gcn3: Free registers when execMask = 0
......................................................................
arch-gcn3: Free registers when execMask = 0
Flat instructions free some of their registers through a call to
scheduleWriteOperandsFromLoad(), which is executed in
GlobalMemPipeline::exec.
When execMask is 0, the instruction returns without issuing a memory
request.
This patch adds in a call to scheduleWriteOperandsFromLoad() when execMask
is 0 for Flat instructions that are either Loads or AtomicReturns, as those
are the instructions that call scheduleWriteOperandsFromLoad() in the memory
pipeline.
This patch also adds in a missing return statement when execMask is 0 in one
of the Flat instructions.
Change-Id: I09296adb7401e7515d3cedceb780a5df4598b109
---
M src/arch/gcn3/insts/instructions.cc
1 file changed, 74 insertions(+), 0 deletions(-)
diff --git a/src/arch/gcn3/insts/instructions.cc
b/src/arch/gcn3/insts/instructions.cc
index 6e81e2c..cc8a9fb 100644
--- a/src/arch/gcn3/insts/instructions.cc
+++ b/src/arch/gcn3/insts/instructions.cc
@@ -39406,6 +39406,9 @@
wf->decLGKMInstsIssued();
wf->rdGmReqsInPipe--;
wf->rdLmReqsInPipe--;
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vfg[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
return;
}
@@ -39504,6 +39507,9 @@
wf->decLGKMInstsIssued();
wf->rdGmReqsInPipe--;
wf->rdLmReqsInPipe--;
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vfg[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
return;
}
@@ -39602,6 +39608,9 @@
wf->decLGKMInstsIssued();
wf->rdGmReqsInPipe--;
wf->rdLmReqsInPipe--;
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vfg[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
return;
}
@@ -39672,6 +39681,9 @@
wf->decLGKMInstsIssued();
wf->rdGmReqsInPipe--;
wf->rdLmReqsInPipe--;
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vfg[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
return;
}
@@ -39742,6 +39754,9 @@
wf->decLGKMInstsIssued();
wf->rdGmReqsInPipe--;
wf->rdLmReqsInPipe--;
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vfg[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
return;
}
@@ -39821,6 +39836,10 @@
wf->decLGKMInstsIssued();
wf->rdGmReqsInPipe--;
wf->rdLmReqsInPipe--;
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vfg[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ return;
}
gpuDynInst->execUnitId = wf->execUnitId;
@@ -40355,6 +40374,11 @@
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vfg[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
@@ -40457,6 +40481,11 @@
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vfg[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
@@ -40560,6 +40589,11 @@
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vfg[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
@@ -40650,6 +40684,11 @@
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vfg[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
@@ -40914,6 +40953,11 @@
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vfg[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
@@ -41004,6 +41048,11 @@
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vfg[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
@@ -41123,6 +41172,11 @@
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vfg[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
@@ -41227,6 +41281,11 @@
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vfg[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
@@ -41319,6 +41378,11 @@
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vfg[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
@@ -41593,6 +41657,11 @@
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vfg[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
@@ -41686,6 +41755,11 @@
wf->decLGKMInstsIssued();
wf->wrGmReqsInPipe--;
wf->rdGmReqsInPipe--;
+ if (instData.GLC) {
+ gpuDynInst->exec_mask = wf->execMask();
+ wf->computeUnit->vfg[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+ }
return;
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/32234
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I09296adb7401e7515d3cedceb780a5df4598b109
Gerrit-Change-Number: 32234
Gerrit-PatchSet: 1
Gerrit-Owner: Kyle Roarty <[email protected]>
Gerrit-MessageType: newchange
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