Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31274 )
Change subject: arch-arm: AddressSize check on translateMmuOff for AArch64
only
......................................................................
arch-arm: AddressSize check on translateMmuOff for AArch64 only
Motivation:
An AddressSizeFault on AArch32 can only happen during a table walk
since the register used as a base by LD/ST is always 32 bit wide.
On AArch64 on the other hand, addresses can be 64bit wide;
when MMU is off (no virtual memory) an invalid physical address
can be specified
Change-Id: Id3ef170e99202c6b0b511fa7205c754956861720
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/tlb.cc
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index db0d55c..ca97849 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1018,21 +1018,23 @@
if (isSecure)
req->setFlags(Request::SECURE);
- bool selbit = bits(vaddr, 55);
- TCR tcr1 = tc->readMiscReg(MISCREG_TCR_EL1);
- int topbit = computeAddrTop(tc, selbit, is_fetch, tcr1, currEL(tc));
- int addr_sz = bits(vaddr, topbit, MaxPhysAddrRange);
- if (addr_sz != 0){
- Fault f;
- if (is_fetch)
- f = std::make_shared<PrefetchAbort>(vaddr,
- ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
- else
- f = std::make_shared<DataAbort>( vaddr,
- TlbEntry::DomainType::NoAccess,
- is_atomic ? false : mode==Write,
- ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
- return f;
+ if (aarch64) {
+ bool selbit = bits(vaddr, 55);
+ TCR tcr1 = tc->readMiscReg(MISCREG_TCR_EL1);
+ int topbit = computeAddrTop(tc, selbit, is_fetch, tcr1,
currEL(tc));
+ int addr_sz = bits(vaddr, topbit, MaxPhysAddrRange);
+ if (addr_sz != 0){
+ Fault f;
+ if (is_fetch)
+ f = std::make_shared<PrefetchAbort>(vaddr,
+ ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+ else
+ f = std::make_shared<DataAbort>( vaddr,
+ TlbEntry::DomainType::NoAccess,
+ is_atomic ? false : mode==Write,
+ ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+ return f;
+ }
}
// @todo: double check this (ARM ARM issue C B3.2.1)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id3ef170e99202c6b0b511fa7205c754956861720
Gerrit-Change-Number: 31274
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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