Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30134 )
Change subject: cpu, sim: Add faulting flag to instruction tracing interface
......................................................................
cpu, sim: Add faulting flag to instruction tracing interface
This patch adds a faulting flag to InstRecord and populates it
accordingly in atomic, timing, minor and o3 CPU models. This
allows tracers to identify that the traced instruction has
faulted, when ExecFaulting is enabled. It can be set with
InstRecord::setFaulting() and read with Instrecord::getFaulting().
This patch also fixes the minor CPU model which was not respecting
the ExecFaulting flag, which is now checked before calling dump() on
the tracing object, to bring it in line with the other CPU models.
Change-Id: I390392d59de930533eab101e96dc4d3c76500748
---
M src/sim/insttracer.hh
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index 2e9806d..1cca3e1 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, 2017 ARM Limited
+ * Copyright (c) 2014, 2017, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -143,6 +143,12 @@
*/
bool predicate;
+ /**
+ * Did the execution of this instruction fault? (requires ExecFaulting
+ * to be enabled)
+ */
+ bool faulting;
+
public:
InstRecord(Tick _when, ThreadContext *_thread,
const StaticInstPtr _staticInst,
@@ -151,7 +157,8 @@
: when(_when), thread(_thread), staticInst(_staticInst), pc(_pc),
macroStaticInst(_macroStaticInst), addr(0), size(0), flags(0),
fetch_seq(0), cp_seq(0), data_status(DataInvalid),
mem_valid(false),
- fetch_seq_valid(false), cp_seq_valid(false), predicate(true)
+ fetch_seq_valid(false), cp_seq_valid(false), predicate(true),
+ faulting(false)
{ }
virtual ~InstRecord()
@@ -218,6 +225,8 @@
void setPredicate(bool val) { predicate = val; }
+ void setFaulting(bool val) { faulting = val; }
+
virtual void dump() = 0;
public:
@@ -241,6 +250,8 @@
InstSeqNum getCpSeq() const { return cp_seq; }
bool getCpSeqValid() const { return cp_seq_valid; }
+
+ bool getFaulting(void) { return faulting; };
};
class InstTracer : public SimObject
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I390392d59de930533eab101e96dc4d3c76500748
Gerrit-Change-Number: 30134
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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