Hello! Well, I have trouble gnetlist (and in turn gsch2pcb as well) processing project with "flat" or common refdefs across all schematics.
That is... I have several symbols with 'source' attribute in top level schem. Each source is unique (copy), and to minimize components I autonumbered components across whole schematic (with slotting enabled). Now some sub-schematics share slotted ICs, but gnetlist doesn't quite see it that way, since it prefixes all sub-schem elements with "hierarchy tag", breaking slotting. In addition, presumably "global symbols" as GND and Vcc are prefixed as well, so I end up with different GND net for every schematic. I presume there isn't much I can do (with current gnetlist) to avoid prefixing (without changing schematics a lot), though a flag for gnetlist or schematic attribute to prevent hierarchical prefixing would be nice. Has anyone having/had the same problem? Anyone willing to do some gnetlist hacking? I probably could "patch" the code, but I don't know my way around gnetlist well enough (yet). _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
