On Feb 28, 2010, at 10:30 AM, Facundo Ferrer wrote: > Hi I was working on my thesis project and I'm designing a 6-bit flash > converter. The circuit has 63 comparators (made by me) , 63 inverters > (made by me) and 1 decoder (126 inputs and 6 outputs, also made by me). > I have a source file for each component (actually more than 127 files > because the decoder has nand gates made by me).
127 files? That's the hard way. Should just need 63 instances of a comparator described by one file, for example. > When I try to check my > circuit with drc or drc2 gnetlist finished with a buffer overflow. Put the following in your gnetlistrc file: (debug-options (list 'stack 200000)) (eval-options (list 'stack 200000)) That should prevent overflow. Our DRC isn't really intended for this kind of circuit. > I > don't know how to solve this. Also, I tried with spice-sdb but gnetlist > finish with Killed. > Here are the links of the output: > - using drc: [1]http://pastebin.com/GrJL6pi9 > - using drc2: [2]http://pastebin.com/UnYk1f8a > - using spice-sdb: [3]http://pastebin.com/MpWjqVq8 > If you need my schematics I will send you. It looks like you're using the kind of hierarchy suitable for a printed circuit flow, not a SPICE/ASIC flow. I suggest first reading the excellent tutorial at http://www.brorson.com/gEDA/SPICE/intro.html. For ASIC, I modify Stuart's flow by leaving out the file= attributes on the symbols, preventing hierarchy expansion. I make a SPICE netlist of each subcircuit separately, and concatenate them to make the design file. That way, a 6000 transistor design needs only a 400 line netlist. A Makefile to coordinate these machinations is useful. > Thanks! Good luck! It'll be fun to have another gEDA ASIC designer around. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
