Dan McMahill wrote: I'd think it would be easy > enough to create a symbol where the bulk terminal is an implicit > connection like some of the digital chips have already. Just be sure > that you are sure of the right names. I'd think this would be > compatible with the existing flow, but perhaps I'm missing something.
I think its about SPICE netlist depending on pinseq, and pinseq depends on having a pin, or does it? Could you make a FET source terminal be a pin with name S and pinseq=3 and somehow have a pinseq=4 related to the substrate without having another pin? He doesn't want to lose substrate in the netlist, just tie it to S for this particular "part" or transistor layout. John Griessen _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
