Hello again,
I've been playing around with $realtobits and $bitstoreal,
and I've found things aren't as clean as I'd hoped.
Basically, I want to simulate floating point operations in my modules.
I figured the process would be:
(1) Convert a real to bits and pass those as an input to a module.
(2) Convert the input to a real (without needing a variable).
(3) Perform an operation.
(3) Convert result of the operation to bits and output.
Here are some problems I've found.
///////////// [ 1 ] /////////////
The following compiles
(and probably shouldn't, unfortunately):
module reals;
wire [63:0] blah = $realtobits(6.35e25);
endmodule
but when run produces:
./a.out:7: syntax error
///////////// [ 2 ] /////////////
The following compiles:
module reals;
SomeModule someModule
(
$realtobits(3.14+3.15)
);
endmodule
module SomeModule
(
input [63:0] in
);
endmodule
but when run produces:
internal error: 13vvp_arith_sum: recv_real(3.140000) not
implemented
../../src/vvp/vvp_net.cc:1386: failed assertion `0'
Abort trap
Seems like the parse tree is a bit out of whack.
Since this doesn't work, neither does something like this:
$realtobits($bitstoreal(arg1)+$bitstoreal(arg2))
///////////// [ 3 ] /////////////
There was some problem with realtobits/bitstoreal that
was fixed with the following change:
Index: vvp/vpi_tasks.cc
===================================================================
RCS file: /home/demon/anoncvs/verilog/vvp/vpi_tasks.cc,v
retrieving revision 1.35
diff -u -r1.35 vpi_tasks.cc
--- vvp/vpi_tasks.cc 12 Apr 2007 04:45:53 -0000 1.35
+++ vvp/vpi_tasks.cc 28 Apr 2007 03:25:34 -0000
@@ -577,7 +577,7 @@
vpip_cur_task = (struct __vpiSysTaskCall*)ref;
if (vpip_cur_task->defn->info.calltf) {
- assert(vpi_mode_flag == VPI_MODE_NONE);
+ /*assert(vpi_mode_flag == VPI_MODE_NONE);*/
vpi_mode_flag = VPI_MODE_CALLTF;
vpip_cur_task->defn->info.calltf(vpip_cur_task->defn-
>info.user_data);
vpi_mode_flag = VPI_MODE_NONE;
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