Günter Dannoritzer wrote:
Hi,
Is anybody using Icarus Verilog for post synthesis simulation?
I have had better success with gplcver for this phase. At least in 0.8x
specify block support in icarus seems unusual.
john
Is there a way to compile the SIMPRIM library from Xilinx into a library
file or does that need to be compiled every time again from scratch when
running the compilation?
Also, does the iSDF plugin support all the primitives generated by
Xilinx tools?
Thanks for the help.
Cheers,
Guenter
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