https://gcc.gnu.org/g:77da4618ce014477d59b738cbd11434789615801
commit r16-5536-g77da4618ce014477d59b738cbd11434789615801 Author: GCC Administrator <[email protected]> Date: Mon Nov 24 00:18:45 2025 +0000 Daily bump. Diff: --- gcc/ChangeLog | 52 +++++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/testsuite/ChangeLog | 21 ++++++++++++++++++++ libgm2/ChangeLog | 6 ++++++ 4 files changed, 80 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7bb19080aa98..7b5232667ebb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,55 @@ +2025-11-23 John David Anglin <[email protected]> + + * config/pa/pa64-linux.h (GLIBC_DYNAMIC_LINKER): Define. + +2025-11-23 John David Anglin <[email protected]> + + PR target/113932 + PR target/113933 + * config/pa/pa.opt (mlra): Default to LRA instead of reload. + +2025-11-23 John David Anglin <[email protected]> + + * config/pa/pa.cc (pa_print_operand): Use REG_POINTER + flag to select base and index registers on targets with + non-equivalent space registers. + (pa_legitimate_address_p): Don't allow scaled and unscaled + indexed addresses until reload is complete. Allow any + register order in unscaled addresses as long as the + REG_POINTER flag is correctly set/unset in the base/index + registers. + * config/pa/predicates.md (mem_operand): Remove code to + delay creating move insns with unscaled indexed addresses + until CSE is not expected. + (move_src_operand): Likewise. + +2025-11-23 Andrew Pinski <[email protected]> + + * match.pd (1/x): Use fold_before_rtl_expansion_p. + (`(m1 CMP m2) * d`): Likewise. + +2025-11-23 Pan Li <[email protected]> + + * match.pd: Remove unnecessary outer convert and add + c for the outer bit_ior. + +2025-11-23 Pan Li <[email protected]> + + * match.pd: Add simplfy to fold outer convert of bit_op + to inner captures. + +2025-11-23 Kugan Vivekanandarajah <[email protected]> + + * ipa-split.cc (pass_split_functions::gate): Do not run when + flag_auto_profile. + (pass_feedback_split_functions::gate): Run when flag_auto_profile. + +2025-11-23 Kugan Vivekanandarajah <[email protected]> + + * tree-ssa-loop-im.cc (is_self_write): New. + (ref_indep_loop_p): Allow hoisting when aliasing references + form a self write pattern. + 2025-11-22 Jeff Law <[email protected]> PR rtl-optimization/122701 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index aaefa8d123a9..0b7cf952dab0 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20251123 +20251124 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ebb818bbb2ca..ea79fd5d1d22 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,24 @@ +2025-11-23 Pan Li <[email protected]> + + * gcc.dg/tree-ssa/bit_op_cvt.1.c: New test. + * gcc.dg/tree-ssa/bit_op_cvt.2.c: New test. + * gcc.dg/tree-ssa/bit_op_cvt.3.c: New test. + * gcc.dg/tree-ssa/bit_op_cvt.4.c: New test. + * gcc.dg/tree-ssa/bit_op_cvt.5.c: New test. + * gcc.dg/tree-ssa/bit_op_cvt.6.c: New test. + * gcc.dg/tree-ssa/bit_op_cvt.h: New test. + +2025-11-23 Kugan Vivekanandarajah <[email protected]> + + * gcc.dg/vect/vect-licm-hoist-1.c: New. + * gcc.dg/vect/vect-licm-hoist-2.c: Likewise. + +2025-11-23 Sandra Loosemore <[email protected]> + + * c-c++-common/gomp/delim-declare-variant-6.c (f3): Use "x86" + instead of "x86_64" in the arch selector, to match both 64- and + 32-bit targets. + 2025-11-22 Nathaniel Shead <[email protected]> PR c++/122636 diff --git a/libgm2/ChangeLog b/libgm2/ChangeLog index f16c52552f36..6dac0eab683a 100644 --- a/libgm2/ChangeLog +++ b/libgm2/ChangeLog @@ -1,3 +1,9 @@ +2025-11-23 Gaius Mulley <[email protected]> + + PR modula2/122801 + * configure: Regenerate. + * configure.ac (libtool_VERSION): Assign to 21:0:0. + 2025-11-03 Sam James <[email protected]> * configure: Regenerate.
