https://gcc.gnu.org/g:b4a55fee48b1cd2bceb528da3b1d58af22e0ce18

commit r15-10506-gb4a55fee48b1cd2bceb528da3b1d58af22e0ce18
Author: GCC Administrator <[email protected]>
Date:   Thu Nov 13 00:26:55 2025 +0000

    Daily bump.

Diff:
---
 gcc/ChangeLog           | 66 +++++++++++++++++++++++++++++++++++++++++++
 gcc/DATESTAMP           |  2 +-
 gcc/ada/ChangeLog       | 12 ++++++++
 gcc/testsuite/ChangeLog | 74 +++++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 153 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e2eed49a6fb7..6b62f5712250 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,69 @@
+2025-11-12  Christophe Lyon  <[email protected]>
+
+       Backported from master:
+       2025-11-12  Christophe Lyon  <[email protected]>
+                   Richard Earnshaw  <[email protected]>
+
+       PR target/122175
+       * config/arm/iterators.md (asm_const_size): New mode attr.
+       * config/arm/mve.md (@mve_<mve_insn>q_n_<supf><mode>): Use it.
+
+2025-11-12  Christophe Lyon  <[email protected]>
+
+       PR target/122189
+       * config/arm/iterators.md (VxCIQ_carry, VxCIQ_M_carry, VxCQ_carry)
+       (VxCQ_M_carry): New iterators.
+       * config/arm/mve.md (get_fpscr_nzcvqc, set_fpscr_nzcvqc): Use
+       unspec instead of unspec_volatile.
+       (vadciq, vadciq_m, vadcq, vadcq_m): Use vfpcc in operation.  Use a
+       different unspec code for carry calcultation.
+       * config/arm/unspecs.md (VADCQ_U_carry, VADCQ_M_U_carry)
+       (VADCQ_S_carry, VADCQ_M_S_carry, VSBCIQ_U_carry ,VSBCIQ_S_carry
+       ,VSBCIQ_M_U_carry ,VSBCIQ_M_S_carry ,VSBCQ_U_carry ,VSBCQ_S_carry
+       ,VSBCQ_M_U_carry ,VSBCQ_M_S_carry ,VADCIQ_U_carry
+       ,VADCIQ_M_U_carry ,VADCIQ_S_carry ,VADCIQ_M_S_carry): New unspec
+       codes.
+
+2025-11-12  Hu, Lin1  <[email protected]>
+
+       Backported from master:
+       2025-11-12  Hu, Lin1  <[email protected]>
+
+       PR target/122446
+       * config/i386/amxavx512intrin.h (_tile_cvtrowps2bf16hi_internal):
+       Input register name by inline asm %c[...], and remove %% before tmm
+       from intel side.
+       (_tile_cvtrowps2bf16li_internal): Ditto.
+       * config/i386/amxbf16intrin.h (_tile_dpbf16ps_internal): Ditto
+       * config/i386/amxcomplexintrin.h (_tile_cmmimfp16ps_internal): Ditto
+       (_tile_cmmrlfp16ps_internal): Ditto
+       (_tile_cmmimfp16ps): Ditto
+       (_tile_cmmrlfp16ps): Ditto
+       * config/i386/amxfp16intrin.h (_tile_dpfp16ps_internal): Ditto
+       (_tile_dpfp16ps): Ditto
+       * config/i386/amxfp8intrin.h (_tile_dpbf8ps_internal): Ditto
+       (_tile_dpbhf8ps_internal): Ditto
+       (_tile_dphbf8ps_internal): Ditto
+       (_tile_dphf8ps_internal): Ditto
+       (_tile_dpbf8ps): Ditto
+       (_tile_dpbhf8ps): Ditto
+       (_tile_dphbf8ps): Ditto
+       (_tile_dphf8ps): Ditto
+       * config/i386/amxint8intrin.h (_tile_int8_dp_internal): Ditto
+       * config/i386/amxmovrsintrin.h (_tile_loaddrs_internal): Ditto
+       (_tile_loaddrst1_internal): Ditto
+       (_tile_loaddrs): Ditto
+       (_tile_loaddrst1): Ditto
+       * config/i386/amxtf32intrin.h (_tile_mmultf32ps_internal): Ditto
+       * config/i386/amxtileintrin.h (_tile_loadd): Ditto
+       (_tile_loadd_internal): Ditto
+       (_tile_stream_loadd): Ditto
+       (_tile_stream_loadd_internal): Ditto
+       (_tile_stored): Ditto
+       (_tile_stored_internal): Ditto
+       (_tile_zero): Ditto
+       (_tile_zero_internal): Ditto
+
 2025-11-11  Jakub Jelinek  <[email protected]>
 
        Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 51fb8be9fa5c..9754f38b48dc 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20251112
+20251113
diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
index abfd31509254..daa46a1f3639 100644
--- a/gcc/ada/ChangeLog
+++ b/gcc/ada/ChangeLog
@@ -1,3 +1,15 @@
+2025-11-12  Eric Botcazou  <[email protected]>
+
+       PR ada/122640
+       * sem_ch3.adb (Analyze_Object_Declaration): Set Is_True_Constant
+       on entry for constants and Never_Set_In_Source in all cases.
+       If an initialization expression is present, set Has_Initial_Value
+       and Is_True_Constant on variables.
+
+2025-11-12  Ronan Desplanques  <[email protected]>
+
+       * sem_ch3.adb (Analyze_Object_Declaration): Call Mutate_Ekind earlier.
+
 2025-11-04  Bob Duff  <[email protected]>
 
        PR ada/118208
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 53964b29fbd0..0dac314cc747 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,77 @@
+2025-11-12  Christophe Lyon  <[email protected]>
+
+       Backported from master:
+       2025-11-12  Christophe Lyon  <[email protected]>
+
+       PR target/122175
+       * gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c: Adjust expected
+       output.
+       * gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vorrq_n_s16.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vorrq_n_u16.c: Likewise.
+
+2025-11-12  Christophe Lyon  <[email protected]>
+
+       Backported from master:
+       2025-11-12  Christophe Lyon  <[email protected]>
+                   Richard Earnshaw  <[email protected]>
+
+       PR target/122175
+       * gcc.target/arm/mve/intrinsics/pr122175.c: New test.
+
+2025-11-12  Christophe Lyon  <[email protected]>
+
+       PR target/122189
+       * gcc.target/arm/mve/intrinsics/vadcq-check-carry.c: New test.
+       * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Adjust instructions
+       order.
+       * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Likewise.
+       * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Likewise.
+       (cherry picked from commits
+       027205879733933ec991c230795da6c01ac50029 and
+       697ccadd7217316ea91ddd978ddc944e6df09522)
+
+2025-11-12  Eric Botcazou  <[email protected]>
+
+       * gnat.dg/warn34.adb: New test.
+
+2025-11-12  Hu, Lin1  <[email protected]>
+
+       Backported from master:
+       2025-11-12  Hu, Lin1  <[email protected]>
+
+       PR target/122446
+       * gcc.target/i386/amxbf16-asmintel-1.c: Modify dg-final to check intel
+       form.
+       * gcc.target/i386/amxcomplex-asmintel-1.c: Ditto.
+       * gcc.target/i386/amxfp16-asmintel-1.c: Ditto.
+       * gcc.target/i386/amxfp8-asmintel-1.c: Ditto.
+       * gcc.target/i386/amxint8-asmintel-1.c: Ditto.
+       * gcc.target/i386/amxmovrs-asmintel-1.c: Ditto.
+       * gcc.target/i386/amxtf32-asmintel-1.c: Ditto.
+       * gcc.target/i386/amxtile-asmintel-1.c: Ditto.
+       * g++.target/i386/pr122446-1.C: New test.
+       * g++.target/i386/pr122446-amxavx512.C: Ditto.
+       * g++.target/i386/pr122446-amxbf16.C: Ditto.
+       * g++.target/i386/pr122446-amxcomplex.C: Ditto.
+       * g++.target/i386/pr122446-amxfp16.C: Ditto.
+       * g++.target/i386/pr122446-amxfp8.C: Ditto.
+       * g++.target/i386/pr122446-amxint8.C: Ditto.
+       * g++.target/i386/pr122446-amxmovrs.C: Ditto.
+       * g++.target/i386/pr122446-amxtf32.C: Ditto.
+       * g++.target/i386/pr122446-amxtile.C: Ditto.
+
 2025-11-11  Lulu Cheng  <[email protected]>
 
        Backported from master:

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