https://gcc.gnu.org/g:fc12a4d6a854bafb5db8218aada66a19743e79ac
commit r16-766-gfc12a4d6a854bafb5db8218aada66a19743e79ac
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Wed May 21 00:17:57 2025 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 81 +++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/cobol/ChangeLog | 39 +++++++++++
gcc/cp/ChangeLog | 17 +++++
gcc/testsuite/ChangeLog | 173 ++++++++++++++++++++++++++++++++++++++++++++++++
libgcc/ChangeLog | 16 +++++
libgcobol/ChangeLog | 20 ++++++
libstdc++-v3/ChangeLog | 64 ++++++++++++++++++
8 files changed, 411 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3236c32f347f..467cdc90752e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,84 @@
+2025-05-20 Andrew Pinski <quic_apin...@quicinc.com>
+
+ * Makefile.in (gimple-match-exports.o-warn): Remove.
+ * gimple-match-exports.cc (gimple_extract): Remove valueize_condition
+ argument.
+ (gimple_extract_op): Update call to gimple_extract.
+ (gimple_simplify): Likewise. Also remove valueize_condition lambda.
+
+2025-05-20 Umesh Kalappa <ukalappa.m...@gmail.com>
+
+ * config/riscv/mips-p8700.md (mips_p8700_dummies): New
+ reservation.
+ (mips_p8700_unknown): Reservation for all the dummies.
+
+2025-05-20 Umesh Kalappa <ukalappa.m...@gmail.com>
+
+ * config/riscv/mips-p8700.md: New scheduler model.
+ * config/riscv/riscv-cores.def (mips-p87000): New tuning model
+ and core architecture.
+ * config/riscv/riscv-opts.h (riscv_microarchitecture_type); Add
+ mips-p8700.
+ * config/riscv/riscv.cc (mips_p8700_tune_info): New uarch
+ tuning parameters.
+ * config/riscv/riscv.md (tune): Add mips_p8700.
+ Include mips-p8700.md
+ * doc/invoke.texi: Document tune/cpu options for the MIPS P8700.
+ Co-authored-by: Jeff Law <j...@ventanamicro.com>
+
+2025-05-20 Jakub Jelinek <ja...@redhat.com>
+
+ * tree-chrec.cc (convert_affine_scev): Use signed_type_for instead of
+ build_nonstandard_integer_type.
+
+2025-05-20 Jakub Jelinek <ja...@redhat.com>
+
+ * gimple-lower-bitint.cc (bitint_big_endian): New variable.
+ (bitint_precision_kind): Set it.
+ (struct bitint_large_huge): Add unsigned argument to
+ finish_arith_overflow.
+ (bitint_large_huge::limb_access_type): Handle bitint_big_endian.
+ (bitint_large_huge::handle_operand): Likewise.
+ (bitint_large_huge::handle_cast): Likewise.
+ (bitint_large_huge::handle_bit_field_ref): Likewise.
+ (bitint_large_huge::handle_load): Likewise.
+ (bitint_large_huge::lower_shift_stmt): Likewise.
+ (bitint_large_huge::finish_arith_overflow): Likewise.
+ Add nelts argument.
+ (bitint_large_huge::lower_addsub_overflow): Handle bitint_big_endian.
+ Adjust finish_arith_overflow caller.
+ (bitint_large_huge::lower_mul_overflow): Likewise.
+ (bitint_large_huge::lower_bit_query): Handle bitint_big_endian.
+ (bitint_large_huge::lower_stmt): Likewise.
+ (build_bitint_stmt_ssa_conflicts): Likewise.
+ (gimple_lower_bitint): Likewise.
+
+2025-05-20 Jeff Law <j...@ventanamicro.com>
+
+ * config/riscv/bitmanip.md (various splits): Avoid writing the output
+ more than once when trivially possible.
+
+2025-05-20 liuhongt <hongtao....@intel.com>
+
+ PR tree-optimization/103771
+ * match.pd (cond_expr_convert_p): Extend the match to handle
+ REAL_CST.
+ * tree-vect-patterns.cc
+ (vect_recog_cond_expr_convert_pattern): Handle REAL_CST.
+
+2025-05-20 Pan Li <pan2...@intel.com>
+
+ * config/riscv/autovec-opt.md: Leverage the new add func to
+ expand the vx insn.
+ * config/riscv/riscv-protos.h (expand_vx_binary_vec_dup_vec): Add
+ new func decl to expand format v = vop(vec_dup(x), v).
+ (expand_vx_binary_vec_vec_dup): Diito but for format
+ v = vop(v, vec_dup(x)).
+ * config/riscv/riscv-v.cc (expand_vx_binary_vec_dup_vec): Add new
+ func impl to expand vx for v = vop(vec_dup(x), v).
+ (expand_vx_binary_vec_vec_dup): Diito but for another format
+ v = vop(v, vec_dup(x)).
+
2025-05-19 Jeff Law <j...@ventanamicro.com>
PR target/120333
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 4ea9877f3b77..2427fe6e152d 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250520
+20250521
diff --git a/gcc/cobol/ChangeLog b/gcc/cobol/ChangeLog
index edacef423749..44bf89fcb1aa 100644
--- a/gcc/cobol/ChangeLog
+++ b/gcc/cobol/ChangeLog
@@ -1,3 +1,42 @@
+2025-05-20 Robert Dubner <rdub...@symas.com>
+ James K. Lowden <jklow...@cobolworx.com>
+
+ PR cobol/119770
+ PR cobol/119772
+ PR cobol/119790
+ PR cobol/119771
+ PR cobol/119810
+ PR cobol/119335
+ PR cobol/119632
+ * cdf-copy.cc (GLOB_BRACE): Eliminate <glob.h>.
+ * cdfval.h (_CDF_VAL_H_): Switch to C++ headers.
+ * copybook.h (class copybook_elem_t): Eliminate <glob.h>.
+ (class copybook_t): Likewise.
+ * gcobc: Numerous changes to improve utility.
+ * gcobol.1: Correct names in the list of functions.
+ * genapi.cc (compare_binary_binary): Use has_attr() function.
+ * lexio.cc (cdftext::lex_open): Typo; filename logic.
+ (cdftext::process_file): Filename logic.
+ * parse.y: Numerous parsing changes.
+ * parse_ante.h (new_alphanumeric): C++ includes; changes to temporaries.
+ (new_tempnumeric): Likewise.
+ (new_tempnumeric_float): Likewise.
+ (set_real_from_capacity): Created.
+ * scan.l: Use yy_pop_state().
+ * scan_ante.h (typed_name): Find figconst from data.initial.
+ * symbols.cc (symbol_valid_udf_args): Eliminate.
+ (symbols_update): figconst processing.
+ (new_temporary_impl): For functions, set .initial to function name.
+ (temporaries_t::acquire): Likewise.
+ (new_alphanumeric): Likewise.
+ (new_temporary): Likewise.
+ * symbols.h (_SYMBOLS_H_): Use C++ includes.
+ (cbl_figconst_tok): Change handling of figconst.
+ (cbl_figconst_field_of): Change handling of figconst.
+ (symbol_valid_udf_args): Eliminate.
+ * symfind.cc (symbol_match2): Change declaration.
+ (symbol_match): Change declaration.
+
2025-05-18 Mark Wielaard <m...@klomp.org>
* lang.opt.urls: Regenerated.
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 174a36ffc378..5510a9f6807b 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,20 @@
+2025-05-20 Nathaniel Shead <nathanielosh...@gmail.com>
+
+ PR c++/120349
+ * module.cc (trees_out::core_bools): Always mark vtables as
+ DECL_EXTERNAL.
+
+2025-05-20 Nathaniel Shead <nathanielosh...@gmail.com>
+
+ PR c++/120013
+ * module.cc (trees_in::install_entity): Handle re-registering
+ the inner TYPE_DECL of a partial specialisation.
+
+2025-05-20 Nathaniel Shead <nathanielosh...@gmail.com>
+
+ PR c++/120350
+ * rtti.cc (get_tinfo_decl_direct): Mark TREE_ADDRESSABLE.
+
2025-05-16 Ville Voutilainen <ville.voutilai...@gmail.com>
* cp-gimplify.cc (cp_fold): Do the conversion unconditionally, even for
same-type cases.
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 18c1f478de5c..c68ca3cb95a2 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,176 @@
+2025-05-20 Robert Dubner <rdub...@symas.com>
+
+ * cobol.dg/group2/FUNCTION_SQRT__2_.cob: Testcase.
+ * cobol.dg/group2/FUNCTION_SQRT__2_.out: Known-good for the testcase.
+
+2025-05-20 Jakub Jelinek <ja...@redhat.com>
+
+ * gcc.dg/torture/bitint-78.c: New test.
+ * gcc.dg/torture/bitint-79.c: New test.
+ * gcc.dg/torture/bitint-80.c: New test.
+ * gcc.dg/torture/bitint-81.c: New test.
+
+2025-05-20 Nathaniel Shead <nathanielosh...@gmail.com>
+
+ PR c++/120349
+ * g++.dg/modules/vtt-3_a.C: New test.
+ * g++.dg/modules/vtt-3_b.C: New test.
+
+2025-05-20 Nathaniel Shead <nathanielosh...@gmail.com>
+
+ PR c++/120013
+ * g++.dg/modules/partial-8.h: New test.
+ * g++.dg/modules/partial-8_a.C: New test.
+ * g++.dg/modules/partial-8_b.C: New test.
+ * g++.dg/modules/partial-8_c.C: New test.
+ * g++.dg/modules/partial-8_d.C: New test.
+
+2025-05-20 Nathaniel Shead <nathanielosh...@gmail.com>
+
+ PR c++/120350
+ * g++.dg/modules/tinfo-3_a.H: New test.
+ * g++.dg/modules/tinfo-3_b.C: New test.
+
+2025-05-20 liuhongt <hongtao....@intel.com>
+
+ * gcc.target/i386/pr103771-5.c: New test.
+ * gcc.target/i386/pr103771-6.c: New test.
+
+2025-05-20 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Extract
+ define T as type for testing.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.
+
+2025-05-20 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Add asm check
+ for vrsub with GR2VR cost 2.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto.
+
+2025-05-20 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Add asm check
+ for vrsub with GR2VR cost 1.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto.
+
+2025-05-20 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Add asm check
+ for vrsub case 1 with GR2VR cost 0.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: Ditto.
+
+2025-05-20 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Add asm check
+ for vrsub with GR2VR cost is 15.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
+
+2025-05-20 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Add vrsub asm
+ dump check.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
+
+2025-05-20 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add vrsub asm check.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test helper
+ macros for vx binary reversed.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
+ data for vrsub.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i16.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i32.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i64.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i8.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u16.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u32.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u64.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u8.c: New test.
+
2025-05-19 Jeff Law <j...@ventanamicro.com>
PR target/120333
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 3f532de19ddd..9f442a8d6a15 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,19 @@
+2025-05-20 Jakub Jelinek <ja...@redhat.com>
+
+ * libgcc-std.ver.in (GCC_14.0.0): Remove bitint related exports
+ from here.
+ * config/i386/libgcc-glibc.ver (GCC_14.0.0): Add them here.
+ * config/i386/libgcc-darwin.ver (GCC_14.0.0): Likewise.
+ * config/i386/libgcc-sol2.ver (GCC_14.0.0): Likewise.
+ * config/aarch64/libgcc-softfp.ver (GCC_14.0.0): Likewise.
+
+2025-05-20 Jakub Jelinek <ja...@redhat.com>
+
+ * libgcc2.c (bitint_reduce_prec): For big endian
+ __LIBGCC_BITINT_ORDER__ use ++*p and --*p instead of
+ ++p and --p.
+ * soft-fp/bitint.h (bitint_reduce_prec): Likewise.
+
2025-05-17 Oleg Endo <olege...@gcc.gnu.org>
* config/sh/lib1funcs.S (ashiftrt_r4_32): Increase alignment.
diff --git a/libgcobol/ChangeLog b/libgcobol/ChangeLog
index 00f697cb7400..83a826eef151 100644
--- a/libgcobol/ChangeLog
+++ b/libgcobol/ChangeLog
@@ -1,3 +1,23 @@
+2025-05-20 Robert Dubner <rdub...@symas.com>
+ James K. Lowden <jklow...@cobolworx.com>
+
+ * charmaps.cc: Switch to C++ includes.
+ * common-defs.h: Likewise.
+ * constants.cc: Likewise.
+ * ec.h: Remove #include <assert.h>.
+ * gcobolio.h (GCOBOLIO_H_): Switch to C++ includes.
+ * gfileio.cc: Likewise.
+ * gmath.cc: Likewise.
+ * intrinsic.cc: Comment formatting; C++ includes.
+ * io.cc: C++ includes.
+ * libgcobol.cc: (__gg__stash_exceptions): Eliminate.
+ * valconv.cc: Switch to C++ includes.
+
+2025-05-20 Robert Dubner <rdub...@symas.com>
+
+ PR cobol/119885
+ * intrinsic.cc: (__gg__sqrt): Change test from <= zero to < zero.
+
2025-05-16 Robert Dubner <rdub...@symas.com>
* common-defs.h (struct cbl_declarative_t): Eliminate blobl.
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 6b4746707451..0276d50550bd 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,67 @@
+2025-05-20 Tomasz Kamiński <tkami...@redhat.com>
+
+ * include/bits/chrono_io.h (_ChronoSpec::_M_locale_specific):
+ Declare as bit fiekd in tail-padding..
+ * include/bits/formatfwd.h (__format::_Align): Defined as enum
+ class and add using enum.
+ * include/std/format (__format::_Pres_type, __format::_Sign)
+ (__format::_WidthPrec, __format::_Arg_t): Defined as enum class
+ and add using enum.
+ (_Pres_type::_Pres_esc): Replace with _Pres_max.
+ (_Pres_type::_Pres_seq, _Pres_type::_Pres_str): Remove.
+ (__format::_Pres_type): Updated values of enumerators as described
+ above.
+ (__format::_Spec): Rearranged members to have 8 bits of tail-padding.
+ (_Spec::_M_debug): Defined.
+ (_Spec::_M_reserved): Extended to 8 bits and moved at the end.
+ (_Spec::_M_reserved2): Removed.
+ (_Spec::_M_parse_fill_and_align, _Spec::_M_parse_sign)
+ (__format::__write_padded_as_spec): Adjusted default value checks.
+ (__format::_Term_char): Add using enum and adjust enumertors.
+ (__Escapes::_S_term): Adjusted for _Term_char values.
+ (__format::__should_escape_ascii): Adjusted _Term_char uses.
+ (__format::__write_escaped): Adjusted for _Term_char.
+ (__formatter_str::parse): Set _Pres_s if specifed and _M_debug
+ instead of _Pres_esc.
+ (__formatter_str::set_debug_format): Set _M_debug instead of
+ _Pres_esc.
+ (__formatter_str::format, __formatter_str::_M_format_range):
+ Check _M_debug instead of _Prec_esc.
+ (__formatter_str::_M_format_escaped): Adjusted _Term_char uses.
+ (__formatter_int::__formatter_int(_Spec<_CharT>)): Set _Pres_d if
+ default presentation type is not set.
+ (__formatter_int::_M_parse): Adjusted default value checks.
+ (__formatter_int::_M_do_parse): Set _M_debug instead of _Pres_esc.
+ (__formatter_int::_M_format_character): Handle escaped presentation.
+ (__formatter_int::_M_format_character_escaped)
+ (__formatter_int::_S_character_width): Merged into
+ _M_format_character.
+ (__formatter_ptr::__formatter_ptr(_Spec<_CharT>)): Set _Pres_p if
+ default presentation type is not set.
+ (__formatter_ptr::parse): Add default __type parameter, store _Pres_p,
+ and handle _M_alt to be consistent with meaning for integers.
+ (__foramtter_ptr<_CharT>::_M_set_default): Define.
+ (__format::__pack_arg_types, std::basic_format_args): Add necessary
+ casts.
+ (formatter<_CharT, _CharT>::set_debug_format)
+ (formatter<char, wchar_t>::set_debug_format): Set _M_debug instead of
+ _Pres_esc.
+ (formatter<_CharT, _CharT>::format, formatter<char, wchar_t>::format):
+ Simplify calls to _M_format_character.
+ (range_formatter<_Rg, _CharT>::parse): Replace _Pres_str with
+ _Pres_s and set _M_debug instead of _Pres_esc.
+ (range_formatter<_Rg, _CharT>::format): Replace _Pres_str with
+ _Pres_s.
+
+2025-05-20 Jonathan Wakely <jwak...@redhat.com>
+
+ * doc/xml/faq.xml: Update URL for archived SGI STL docs.
+ * doc/xml/manual/containers.xml: Likewise.
+ * doc/xml/manual/extensions.xml: Likewise.
+ * doc/xml/manual/using.xml: Likewise.
+ * doc/xml/manual/utilities.xml: Likewise.
+ * doc/html/*: Regenerate.
+
2025-05-19 Jonathan Wakely <jwak...@redhat.com>
* include/std/ranges (_ZipTransform::operator()): Remove name of
