https://gcc.gnu.org/g:5bf7e32c20992007d9046a7e350e00b7cb8e1676
commit r16-378-g5bf7e32c20992007d9046a7e350e00b7cb8e1676
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Mon May 5 00:17:44 2025 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 40 ++++++++++++++++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/fortran/ChangeLog | 10 ++++++++++
gcc/testsuite/ChangeLog | 38 ++++++++++++++++++++++++++++++++++++++
4 files changed, 89 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2814c52783ff..15fbb6205030 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,43 @@
+2025-05-04 Jeff Law <j...@ventanamicro.com>
+
+ * config.gcc (riscv): Add riscv-vect-permcost.o to extra_objs.
+ * config/riscv/riscv-passes.def (pass_vector_permcost): Add new pass.
+ * config/riscv/riscv-protos.h (make_pass_vector_permconst): Declare.
+ * config/riscv/riscv-vect-permconst.cc: New file.
+ * config/riscv/t-riscv: Add build rule for riscv-vect-permcost.o
+
+2025-05-04 Jin Ma <ji...@linux.alibaba.com>
+ Dimitar Dimitrov <dimi...@dinux.eu>
+
+ * config/riscv/riscv.cc (riscv_print_operand): Add H.
+ * doc/extend.texi: Document for H.
+
+2025-05-04 Jeff Law <j...@ventanamicro.com>
+
+ * config/riscv/riscv.cc (riscv_register_move_cost): Handle
+ subclasses with vector registers as well.
+
+2025-05-04 Jan Hubicka <hubi...@ucw.cz>
+
+ PR target/119900
+ * cgraph.cc (cgraph_edge::maybe_hot_p): Add
+ a variant accepting a sreal scale; use reliability of
+ profile.
+ * cgraph.h (cgraph_edge::maybe_hot_p): Declare
+ a varaint accepting a sreal scale.
+ * ipa-inline.cc (callee_speedup): New function.
+ (want_inline_small_function_p): add early return
+ and avoid duplicated lookup of summaries; use scaled
+ maybe_hot predicate.
+
+2025-05-04 Pan Li <pan2...@intel.com>
+
+ * config/riscv/riscv.cc (riscv_emit_frm_mode_set): Refactor
+ the frm mode set by removing fsrmsi_restore_volatile.
+ * config/riscv/vector-iterators.md (unspecv): Remove as
+ unnecessary.
+ * config/riscv/vector.md (fsrmsi_restore_volatile): Ditto.
+
2025-05-03 Jan Hubicka <hubi...@ucw.cz>
* config/i386/i386.cc (unspec_pcmp_p): New function.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e49f2330611b..568be1e3bc4f 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250504
+20250505
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 9b2a48d991f1..f87c64b3afcf 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,13 @@
+2025-05-04 Harald Anlauf <anl...@gmx.de>
+
+ PR fortran/119986
+ * expr.cc (is_subref_array): When searching for array references,
+ do not terminate early so that inquiry references to complex
+ components work.
+ * primary.cc (gfc_variable_attr): A substring reference can refer
+ to either a scalar or array character variable. Adjust search
+ accordingly.
+
2025-05-01 Paul Thomas <pa...@gcc.gnu.org>
PR fortran/119948
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 0d4d715a7eca..8b7e652f2971 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,41 @@
+2025-05-04 Harald Anlauf <anl...@gmx.de>
+
+ PR fortran/119986
+ * gfortran.dg/actual_array_subref.f90: New test.
+
+2025-05-04 Jeff Law <j...@ventanamicro.com>
+
+ * gcc.target/riscv/rvv/vsetvl/avl_prop-2.c: Disable jump threading
+ and adjust number of expected vsetvls as needed.
+ * gcc.target/riscv/rvv/vsetvl/avl_single-56.c: Likewise.
+ * gcc.target/riscv/rvv/vsetvl/avl_single-67.c: Likewise.
+ * gcc.target/riscv/rvv/vsetvl/avl_single-68.c: Likewise.
+ * gcc.target/riscv/rvv/vsetvl/avl_single-71.c: Likewise.
+
+2025-05-04 Jin Ma <ji...@linux.alibaba.com>
+ Dimitar Dimitrov <dimi...@dinux.eu>
+
+ * gcc.target/riscv/modifier-H-error-1.c: New test.
+ * gcc.target/riscv/modifier-H-error-2.c: New test.
+ * gcc.target/riscv/modifier-H.c: New test.
+
+2025-05-04 Jeff Law <j...@ventanamicro.com>
+
+ * gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: Adjust expected
+ output.
+ * gcc.target/riscv/xtheadfmemidx-zfa-medany.c: Likewise.
+ * gcc.target/riscv/xtheadfmv-fmv.c: Skip for -Os and -Oz.
+ * gcc.target/riscv/zfa-fmovh-fmovp.c: Use sifive-p400 tuning.
+
+2025-05-04 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c: Adjust
+ the asm dump check times.
+ * gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c: Ditto.
+ * gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c: Ditto.
+ * gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c: Ditto.
+ * gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c: Ditto.
+
2025-05-03 Jason Merrill <ja...@redhat.com>
PR c++/85944
