https://gcc.gnu.org/g:651c85825a74ca1b4f727f1bd7cf990e9327476a
commit r13-9415-g651c85825a74ca1b4f727f1bd7cf990e9327476a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Thu Mar 6 00:22:12 2025 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 40 ++++++++++++++++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/testsuite/ChangeLog | 37 +++++++++++++++++++++++++++++++++++++
3 files changed, 78 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 82a0124aeb95..fa6c713dabc6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,43 @@
+2025-03-05 Uros Bizjak <ubiz...@gmail.com>
+
+ Backported from master:
+ 2025-03-03 Uros Bizjak <ubiz...@gmail.com>
+
+ PR rtl-optimization/118739
+ * combine.cc (distribute_notes) <case REG_UNUSED>: Correct the
+ logic when the register is used by I3.
+
+2025-03-05 Richard Sandiford <richard.sandif...@arm.com>
+
+ Backported from master:
+ 2025-03-04 Richard Sandiford <richard.sandif...@arm.com>
+
+ PR tree-optimization/118976
+ * fold-const.cc (const_unop): Use ~ rather than - for BIT_NOT_EXPR.
+ * config/aarch64/aarch64.cc (aarch64_test_sve_folding): New function.
+ (aarch64_run_selftests): Run it.
+
+2025-03-05 Richard Sandiford <richard.sandif...@arm.com>
+
+ Backported from master:
+ 2024-10-14 Richard Sandiford <richard.sandif...@arm.com>
+
+ PR target/116999
+ PR target/117045
+ * config/aarch64/aarch64-sve-builtins-base.cc
+ (svwhilelx_impl::fold): Check for WHILELTs of the minimum value
+ and WHILELEs of the maximum value. Fold them to all-false and
+ all-true respectively.
+
+2025-03-05 Richard Sandiford <richard.sandif...@arm.com>
+
+ Backported from master:
+ 2024-08-21 Richard Sandiford <richard.sandif...@arm.com>
+
+ PR testsuite/116238
+ * config/aarch64/aarch64.cc (aarch64_hard_regno_caller_save_mode):
+ Only return SImode if we can convert to and from it.
+
2025-03-02 Jeff Law <j...@ventanamicro.com>
PR target/116720
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 0cf6d8a9f9a9..31df6d356f31 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250305
+20250306
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8404303b0bf1..270ab3f656f0 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,40 @@
+2025-03-05 Jakub Jelinek <ja...@redhat.com>
+
+ Backported from master:
+ 2025-03-04 Jakub Jelinek <ja...@redhat.com>
+
+ PR rtl-optimization/119071
+ * gcc.dg/pr119071.c: New test.
+ * gcc.c-torture/execute/pr119071.c: New test.
+
+2025-03-05 Uros Bizjak <ubiz...@gmail.com>
+
+ Backported from master:
+ 2025-03-03 Uros Bizjak <ubiz...@gmail.com>
+
+ PR rtl-optimization/118739
+ * gcc.target/i386/pr118739.c: New test.
+
+2025-03-05 Richard Sandiford <richard.sandif...@arm.com>
+
+ Backported from master:
+ 2024-10-14 Richard Sandiford <richard.sandif...@arm.com>
+
+ PR target/116999
+ PR target/117045
+ * gcc.target/aarch64/sve/acle/general/whilele_5.c: Fix bogus
+ expected result.
+ * gcc.target/aarch64/sve/acle/general/whilele_11.c: New test.
+ * gcc.target/aarch64/sve/acle/general/whilele_12.c: Likewise.
+
+2025-03-05 Richard Sandiford <richard.sandif...@arm.com>
+
+ Backported from master:
+ 2024-08-21 Richard Sandiford <richard.sandif...@arm.com>
+
+ PR testsuite/116238
+ * gcc.target/aarch64/sve/pr116238.c: New test.
+
2025-03-02 Jeff Law <j...@ventanamicro.com>
PR target/116720
