https://gcc.gnu.org/g:491c0b8071323295471648a438eb4c216d15735c
commit r15-7800-g491c0b8071323295471648a438eb4c216d15735c
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Tue Mar 4 00:18:29 2025 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 82 +++++++++++++++++++++++++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/fortran/ChangeLog | 16 ++++++++++
gcc/po/ChangeLog | 6 ++++
gcc/testsuite/ChangeLog | 37 ++++++++++++++++++++++
libcpp/po/ChangeLog | 6 ++++
6 files changed, 148 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0e63581d372a..d422743d98d0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,85 @@
+2025-03-03 Andrew Carlotti <andrew.carlo...@arm.com>
+
+ * common/config/aarch64/aarch64-common.cc
+ (struct aarch64_extension_info): Add field.
+ (aarch64_get_required_features): New.
+ * config/aarch64/aarch64-builtins.cc
+ (aarch64_simd_switcher::aarch64_simd_switcher): Rename to...
+ (aarch64_target_switcher::aarch64_target_switcher): ...this,
+ and extend to handle sve, nosimd and target pragmas.
+ (aarch64_simd_switcher::~aarch64_simd_switcher): Rename to...
+ (aarch64_target_switcher::~aarch64_target_switcher): ...this,
+ and extend to handle sve, nosimd and target pragmas.
+ (handle_arm_acle_h): Use aarch64_target_switcher.
+ (handle_arm_neon_h): Rename switcher and pass explicit flags.
+ (aarch64_general_init_builtins): Ditto.
+ * config/aarch64/aarch64-protos.h
+ (class aarch64_simd_switcher): Rename to...
+ (class aarch64_target_switcher): ...this, and add new members.
+ (aarch64_get_required_features): New prototype.
+ * config/aarch64/aarch64-sve-builtins.cc
+ (sve_switcher::sve_switcher): Delete
+ (sve_switcher::~sve_switcher): Delete
+ (sve_alignment_switcher::sve_alignment_switcher): New
+ (sve_alignment_switcher::~sve_alignment_switcher): New
+ (register_builtin_types): Use alignment switcher
+ (init_builtins): Rename switcher.
+ (handle_arm_neon_sve_bridge_h): Ditto.
+ (handle_arm_sme_h): Ditto.
+ (handle_arm_sve_h): Ditto, and use alignment switcher.
+ * config/aarch64/aarch64-sve-builtins.h
+ (class sve_switcher): Delete.
+ (class sme_switcher): Delete.
+ (class sve_alignment_switcher): New.
+ * config/aarch64/t-aarch64 (aarch64-builtins.o): Add $(REGS_H).
+ (aarch64-sve-builtins.o): Remove $(REG_H).
+
+2025-03-03 Richard Earnshaw <rearn...@arm.com>
+
+ * config/arm/thumb1.md (split patterns for GEU and LEU): New.
+
+2025-03-03 Uros Bizjak <ubiz...@gmail.com>
+
+ Revert:
+ 2025-03-03 Uros Bizjak <ubiz...@gmail.com>
+
+ * combine.cc (distribute_notes):
+ Reverse negative logic in ternary operators.
+
+2025-03-03 Uros Bizjak <ubiz...@gmail.com>
+
+ * combine.cc (distribute_notes):
+ Reverse negative logic in ternary operators.
+
+2025-03-03 Uros Bizjak <ubiz...@gmail.com>
+
+ PR rtl-optimization/118739
+ * combine.cc (distribute_notes) <case REG_UNUSED>: Correct the
+ logic when the register is used by I3.
+
+2025-03-03 Martin Jambor <mjam...@suse.cz>
+
+ PR ipa/118785
+ * ipa-cp.cc (ipa_vr_intersect_with_arith_jfunc): Handle non-conversion
+ unary operations separately before doing any conversions. Check
+ expr_type_first_operand_type_p for non-unary operations too. Fix type
+ of op_res.
+
+2025-03-03 Richard Biener <rguent...@suse.de>
+
+ PR tree-optimization/119057
+ * tree-vect-loop.cc (check_reduction_path): Add argument
+ specifying whether we're analyzing the inner loop of a
+ double reduction. Do not allow extra uses outside of the
+ double reduction cycle in this case.
+ (vect_is_simple_reduction): Adjust.
+
+2025-03-03 Richard Biener <rguent...@suse.de>
+
+ PR ipa/119067
+ * ipa-devirt.cc (odr_types_equivalent_p): Check
+ TYPE_VECTOR_SUBPARTS for vectors.
+
2025-03-02 Jeff Law <j...@ventanamicro.com>
PR target/118934
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b12838a39432..7b95daf81709 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250303
+20250304
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index d2efacc59225..442fbfce60f4 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,19 @@
+2025-03-03 Harald Anlauf <anl...@gmx.de>
+
+ PR fortran/101577
+ * symbol.cc (verify_bind_c_derived_type): Generate error message
+ for derived type with no components in standard conformance mode,
+ indicating that this is a GNU extension.
+
+2025-03-03 Andre Vehreschild <ve...@gcc.gnu.org>
+
+ PR fortran/118747
+ * trans-array.cc (gfc_trans_array_ctor_element): Remove copy to
+ temporary variable.
+ * trans-expr.cc (gfc_conv_procedure_call): Use references to
+ array members instead of copies when freeing after use.
+ Formatting fix.
+
2025-03-02 Sandra Loosemore <sloosem...@baylibre.com>
* intrinsic.texi: Fix inconsistent capitalization of argument
diff --git a/gcc/po/ChangeLog b/gcc/po/ChangeLog
index 9536c2d76b40..5f2e5026b659 100644
--- a/gcc/po/ChangeLog
+++ b/gcc/po/ChangeLog
@@ -1,3 +1,9 @@
+2025-03-03 Joseph Myers <josmy...@redhat.com>
+
+ * be.po, da.po, de.po, el.po, es.po, fi.po, fr.po, hr.po, id.po,
+ ja.po, ka.po, nl.po, ru.po, sr.po, sv.po, tr.po, uk.po, vi.po,
+ zh_CN.po, zh_TW.po: Update.
+
2025-02-14 Joseph Myers <josmy...@redhat.com>
* gcc.pot: Regenerate.
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b8f065282304..336bf7443c5e 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,40 @@
+2025-03-03 Harald Anlauf <anl...@gmx.de>
+
+ PR fortran/101577
+ * gfortran.dg/empty_derived_type.f90: Adjust dg-options.
+ * gfortran.dg/empty_derived_type_2.f90: New test.
+
+2025-03-03 Richard Earnshaw <rearn...@arm.com>
+
+ * gcc.target/arm/unsigned-extend-1.c: Expand check for any
+ insn suggesting a zero-extend. XFAIL for thumb1 code.
+
+2025-03-03 Uros Bizjak <ubiz...@gmail.com>
+
+ PR rtl-optimization/118739
+ * gcc.target/i386/pr118739.c: New test.
+
+2025-03-03 Martin Jambor <mjam...@suse.cz>
+
+ PR ipa/118785
+ * g++.dg/lto/pr118785_0.C: New test.
+
+2025-03-03 Richard Biener <rguent...@suse.de>
+
+ PR tree-optimization/119057
+ * gcc.dg/vect/pr119057.c: New testcase.
+
+2025-03-03 Richard Biener <rguent...@suse.de>
+
+ PR ipa/119067
+ * g++.dg/lto/pr119067_0.C: New testcase.
+ * g++.dg/lto/pr119067_1.C: Likewise.
+
+2025-03-03 Andre Vehreschild <ve...@gcc.gnu.org>
+
+ PR fortran/118747
+ * gfortran.dg/alloc_comp_auto_array_4.f90: New test.
+
2025-03-02 Gaius Mulley <gaiusm...@gmail.com>
PR modula2/119088
diff --git a/libcpp/po/ChangeLog b/libcpp/po/ChangeLog
index ab3b04b01d10..2ad5b479d75b 100644
--- a/libcpp/po/ChangeLog
+++ b/libcpp/po/ChangeLog
@@ -1,3 +1,9 @@
+2025-03-03 Joseph Myers <josmy...@redhat.com>
+
+ * be.po, ca.po, da.po, de.po, el.po, eo.po, es.po, fi.po, fr.po,
+ id.po, ja.po, ka.po, nl.po, pt_BR.po, ro.po, ru.po, sr.po, sv.po,
+ tr.po, uk.po, vi.po, zh_CN.po, zh_TW.po: Update.
+
2025-02-14 Joseph Myers <josmy...@redhat.com>
* cpplib.pot: Regenerate.
