https://gcc.gnu.org/g:e9bd9d42dddd7a9b1c080426b0b16d3704673cbf
commit r15-7117-ge9bd9d42dddd7a9b1c080426b0b16d3704673cbf
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Wed Jan 22 00:18:57 2025 +0000
Daily bump.
Diff:
---
ChangeLog | 4 ++
gcc/ChangeLog | 147 ++++++++++++++++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/c/ChangeLog | 5 ++
gcc/cp/ChangeLog | 43 ++++++++++++
gcc/testsuite/ChangeLog | 176 ++++++++++++++++++++++++++++++++++++++++++++++++
libphobos/ChangeLog | 6 ++
7 files changed, 382 insertions(+), 1 deletion(-)
diff --git a/ChangeLog b/ChangeLog
index f9d4b64c65ea..5a50100116d8 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,7 @@
+2025-01-21 Alfie Richards <alfie.richa...@arm.com>
+
+ * MAINTAINERS: Add myself to write after approval.
+
2025-01-13 Martin Jambor <mjam...@suse.cz>
* MAINTAINERS: Fix the name order of the Write After Approval section.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 273ec099fe66..38b386b5a25f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,150 @@
+2025-01-21 Jeff Law <j...@ventanamicro.com>
+
+ Revert:
+ 2024-10-29 yulong <shiyul...@iscas.ac.cn>
+
+ * config.gcc: Add riscv_cmo.h.
+ * config/riscv/riscv_cmo.h: New file.
+
+2025-01-21 Andrew Pinski <quic_apin...@quicinc.com>
+
+ PR tree-optimization/118483
+ * match.pd (`x ==/!= ~x`): Allow for an optional convert
+ and use itwise_inverted_equal_p/maybe_bit_not instead of
+ directly matching bit_not.
+
+2025-01-21 Robin Dapp <rd...@ventanamicro.com>
+
+ * config/riscv/riscv.cc (riscv_file_end): Fix format string.
+ (riscv_lshift_subword): Mark MODE as unused.
+
+2025-01-21 Georg-Johann Lay <a...@gjlay.de>
+
+ * config/avr/avr-passes.cc (avr_emit_shift) [ASHIFT,HImode]:
+ Allow offsets 5 and 6 as 3op provided have MUL and a scratch.
+ * config/avr/avr.cc (avr_optimize_size_max_p): New function.
+ (avr_out_ashlhi3_mul): New function.
+ (ashlhi3_out) [case 4, 5, 6]: Better speed for -Os.
+ * config/avr/avr.md (isa) <mul, no_mul>: New attr values.
+ (*ashlhi3_const): Add alternative for offsets 5 and 6.
+
+2025-01-21 Jin Ma <ji...@linux.alibaba.com>
+
+ PR target/116593
+ * config/riscv/constraints.md (vl): New.
+ * config/riscv/thead-vector.md: Replacing rK with rvl.
+ * config/riscv/vector.md: Likewise.
+
+2025-01-21 Denis Chertykov <cherty...@gmail.com>
+
+ * lra-spills.cc (assign_stack_slot_num_and_sort_pseudos): Use known_ge
+ to compare sizes.
+
+2025-01-21 Jeff Law <j...@ventanamicro.com>
+
+ PR target/116256
+ * config/riscv/predicates.md (consecutive_bits_operand): Properly
+ handle (const_int 0).
+
+2025-01-21 Alfie Richards <alfie.richa...@arm.com>
+
+ * config/aarch64/aarch64.opt.urls: Regenerate
+
+2025-01-21 Richard Biener <rguent...@suse.de>
+
+ PR tree-optimization/118569
+ * cfgloopmanip.cc (fix_loop_placement): When the loops
+ nesting parents changed, mark all blocks to be scanned
+ for LC PHI uses.
+ (fix_bb_placements): Remove code moved into fix_loop_placement.
+
+2025-01-21 Vladimir Miloserdov <vladimir.miloser...@arm.com>
+
+ * config/aarch64/aarch64-c.cc
+ (aarch64_update_cpp_builtins): Add new flag TARGET_LUT.
+ * config/aarch64/aarch64-sve-builtins-shapes.cc
+ (struct luti_base): Shape for lut intrinsics.
+ (SHAPE): Specializations for lut shapes for luti2 and luti4..
+ * config/aarch64/aarch64-sve-builtins-shapes.h: Declare lut
+ intrinsics.
+ * config/aarch64/aarch64-sve-builtins-sve2.cc
+ (class svluti_lane_impl): Define expand for lut intrinsics.
+ (FUNCTION): Define expand for lut intrinsics.
+ * config/aarch64/aarch64-sve-builtins-sve2.def
+ (REQUIRED_EXTENSIONS): Declare lut intrinsics behind lut flag.
+ (svluti2_lane): Define intrinsic behind flag.
+ (svluti4_lane): Define intrinsic behind flag.
+ * config/aarch64/aarch64-sve-builtins-sve2.h: Declare lut
+ intrinsics.
+ * config/aarch64/aarch64-sve-builtins.cc
+ (TYPES_bh_data): New type for byte and halfword.
+ (bh_data): Type array for byte and halfword.
+ (h_data): Type array for halfword.
+ * config/aarch64/aarch64-sve2.md
+ (@aarch64_sve_luti<LUTI_BITS><mode>): Instruction patterns for
+ lut intrinsics.
+ * config/aarch64/iterators.md: Iterators and attributes for lut
+ intrinsics.
+
+2025-01-21 Tamar Christina <tamar.christ...@arm.com>
+
+ PR middle-end/118273
+ * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use nvectors when
+ doing mask registrations.
+
+2025-01-21 Tamar Christina <tamar.christ...@arm.com>
+
+ * config.gcc (aarch64-*-elf): Drop ILP32 from default multilibs.
+
+2025-01-21 Lulu Cheng <chengl...@loongson.cn>
+
+ * config/loongarch/loongarch-protos.h
+ (loongarch_reset_previous_fndecl): Add function declaration.
+ (loongarch_save_restore_target_globals): Likewise.
+ (loongarch_register_pragmas): Likewise.
+ * config/loongarch/loongarch-target-attr.cc
+ (loongarch_option_valid_attribute_p): Optimize the processing
+ of attributes.
+ (loongarch_pragma_target_parse): New functions.
+ (loongarch_register_pragmas): Likewise.
+ * config/loongarch/loongarch.cc
+ (loongarch_reset_previous_fndecl): New functions.
+ (loongarch_set_current_function): When the old_tree is the same
+ as the new_tree, the rules for using registers, etc.,
+ are set according to the option values to ensure that the
+ pragma can be processed correctly.
+ * config/loongarch/loongarch.h (REGISTER_TARGET_PRAGMAS):
+ Define macro.
+ * doc/extend.texi: Supplemental Documentation.
+
+2025-01-21 Lulu Cheng <chengl...@loongson.cn>
+
+ * attr-urls.def: Regenerate.
+ * config.gcc: Add loongarch-target-attr.o to extra_objs.
+ * config/loongarch/loongarch-protos.h
+ (loongarch_option_valid_attribute_p): Function declaration.
+ (loongarch_option_override_internal): Likewise.
+ * config/loongarch/loongarch.cc
+ (loongarch_option_override_internal): Delete the modifications
+ to target_option_default_node and target_option_current_node.
+ (loongarch_set_current_function): Add annotation information.
+ (loongarch_option_override): add assignment operations to
+ target_option_default_node and target_option_current_node.
+ (TARGET_OPTION_VALID_ATTRIBUTE_P): Define.
+ * config/loongarch/t-loongarch: Add compilation of target file
+ loongarch-target-attr.o.
+ * doc/extend.texi: Add description information of LoongArch
+ Function Attributes.
+ * config/loongarch/loongarch-target-attr.cc: New file.
+
+2025-01-21 Alfie Richards <alfie.richa...@arm.com>
+
+ * config/aarch64/aarch64.cc
+ (aarch64_process_target_version_attr): Add experimental warning.
+ * config/aarch64/aarch64.opt: Add command line option to disable
+ warning.
+ * doc/invoke.texi: Add documentation for -W[no-]experimental-fmv-target.
+
2025-01-20 Vladimir N. Makarov <vmaka...@redhat.com>
PR target/118560
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 309e1782f83f..b0aec664e8d7 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250121
+20250122
diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog
index 750e9aee9b7e..7d81e07779d9 100644
--- a/gcc/c/ChangeLog
+++ b/gcc/c/ChangeLog
@@ -1,3 +1,8 @@
+2025-01-21 Jakub Jelinek <ja...@redhat.com>
+
+ * c-decl.cc (names_builtin_p): Return 1 for RID_C23_VA_START and
+ RID_VA_ARG.
+
2025-01-16 Sandra Loosemore <sloosem...@baylibre.com>
* c-parser.cc (c_parser_omp_assumption_clauses): Give a more specific
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 555144d3e32d..592434bc417a 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,46 @@
+2025-01-21 Andrew Pinski <quic_apin...@quicinc.com>
+
+ PR c++/118525
+ * cp-gimplify.cc (cp_fold): Check operands of unary, binary,
cond/vec_cond
+ and array_ref for error_mark before checking if the operands had
changed.
+
+2025-01-21 Jakub Jelinek <ja...@redhat.com>
+
+ PR objc++/118586
+ * parser.cc (cp_parser_objc_message_args): Handle CPP_EMBED.
+
+2025-01-21 Marek Polacek <pola...@redhat.com>
+
+ PR c++/118396
+ PR c++/118523
+ * constexpr.cc (cxx_eval_outermost_constant_expr): For non-simple
+ TARGET_EXPRs, return ctx.ctor rather than the result of
+ cxx_eval_constant_expression. If TYPE and the type of R don't
+ match, return the original expression.
+
+2025-01-21 Simon Martin <si...@nasilyan.com>
+
+ PR c++/118225
+ * typeck.cc (build_class_member_access_expr): Let errors that
+ that have been reported go through.
+
+2025-01-21 Jakub Jelinek <ja...@redhat.com>
+
+ * parser.cc (cp_lexer_new_main): Attempt to optimize large sequences
+ of CPP_NUMBER with int type and values 0-255 separated by CPP_COMMA
+ into CPP_EMBED with RAW_DATA_CST u.value.
+
+2025-01-21 Jakub Jelinek <ja...@redhat.com>
+
+ * cp-objcp-common.cc (names_builtin_p): Return 1 for RID_VA_ARG.
+
+2025-01-21 Jakub Jelinek <ja...@redhat.com>
+
+ PR c++/118532
+ * call.cc (add_list_candidates): Handle RAW_DATA_CST among init_list
+ elts.
+ * error.cc (dump_expr_init_vec): Handle RAW_DATA_CST among v elts.
+
2025-01-20 Nathaniel Shead <nathanielosh...@gmail.com>
* parser.cc (cp_parser_decomposition_declaration): Check linkage
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 12a22bbac38a..6ccefdc0d300 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,179 @@
+2025-01-21 Jeff Law <j...@ventanamicro.com>
+
+ Revert:
+ 2024-10-29 yulong <shiyul...@iscas.ac.cn>
+
+ * gcc.target/riscv/cmo-32.c: New test.
+ * gcc.target/riscv/cmo-64.c: New test.
+
+2025-01-21 Andrew Pinski <quic_apin...@quicinc.com>
+
+ PR tree-optimization/118483
+ * gcc.dg/tree-ssa/pr118483-1.c: New test.
+ * gcc.dg/tree-ssa/pr118483-2.c: New test.
+ * gcc.dg/tree-ssa/pr118483-3.c: New test.
+ * gcc.dg/tree-ssa/pr118483-4.c: New test.
+
+2025-01-21 Andrew Pinski <quic_apin...@quicinc.com>
+
+ PR c++/118525
+ * g++.dg/cpp2a/consteval38.C: New test.
+
+2025-01-21 Dimitar Dimitrov <dimi...@dinux.eu>
+
+ * gcc.dg/torture/pr117546.c: Require effective target int32plus.
+
+2025-01-21 Jakub Jelinek <ja...@redhat.com>
+
+ PR objc++/118586
+ * objc.dg/embed-1.m: New test.
+ * obj-c++.dg/embed-1.mm: New test.
+ * obj-c++.dg/va-meth-2.mm: New test.
+
+2025-01-21 Jin Ma <ji...@linux.alibaba.com>
+
+ PR target/116593
+ * g++.target/riscv/rvv/rvv.exp: Enable testsuite of XTheadVector.
+ * g++.target/riscv/rvv/xtheadvector/pr116593.C: New test.
+
+2025-01-21 Jin Ma <ji...@linux.alibaba.com>
+
+ * gcc.target/riscv/rvv/rvv.exp: Enable testsuite of
+ XTheadVector.
+ * gcc.target/riscv/rvv/xtheadvector/pr114194.c: Adjust correctly.
+ * gcc.target/riscv/rvv/xtheadvector/prefix.c: Likewise.
+ * gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: Likewise.
+ * gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: Likewise.
+ * gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: Likewise.
+ * gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: Likewise.
+ * gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: Likewise.
+ * gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: Likewise.
+
+2025-01-21 Jakub Jelinek <ja...@redhat.com>
+
+ PR target/118560
+ * gcc.dg/dfp/pr118560.c: New test.
+
+2025-01-21 Marek Polacek <pola...@redhat.com>
+
+ PR c++/118396
+ PR c++/118523
+ * g++.dg/cpp0x/constexpr-prvalue4.C: New test.
+ * g++.dg/cpp1y/constexpr-prvalue3.C: New test.
+
+2025-01-21 Thomas Schwinge <tschwi...@baylibre.com>
+
+ PR tree-optimization/118211
+ PR tree-optimization/116126
+ * gcc.dg/vect/vect-switch-search-line-fast.c: Update for GCN.
+
+2025-01-21 Richard Biener <rguent...@suse.de>
+
+ PR tree-optimization/118569
+ * gcc.dg/torture/pr118569.c: New testcase.
+
+2025-01-21 Vladimir Miloserdov <vladimir.miloser...@arm.com>
+
+ * gcc.target/aarch64/sve/acle/asm/test_sve_acle.h: New test
+ macro.
+ * lib/target-supports.exp: Add lut flag to the for loop.
+ * gcc.target/aarch64/sve/acle/general-c/lut_1.c: New test.
+ * gcc.target/aarch64/sve/acle/general-c/lut_2.c: New test.
+ * gcc.target/aarch64/sve/acle/general-c/lut_3.c: New test.
+ * gcc.target/aarch64/sve/acle/general-c/lut_4.c: New test.
+ * gcc.target/aarch64/sve2/acle/asm/luti2_bf16.c: New test.
+ * gcc.target/aarch64/sve2/acle/asm/luti2_f16.c: New test.
+ * gcc.target/aarch64/sve2/acle/asm/luti2_s16.c: New test.
+ * gcc.target/aarch64/sve2/acle/asm/luti2_s8.c: New test.
+ * gcc.target/aarch64/sve2/acle/asm/luti2_u16.c: New test.
+ * gcc.target/aarch64/sve2/acle/asm/luti2_u8.c: New test.
+ * gcc.target/aarch64/sve2/acle/asm/luti4_bf16.c: New test.
+ * gcc.target/aarch64/sve2/acle/asm/luti4_bf16_x2.c: New test.
+ * gcc.target/aarch64/sve2/acle/asm/luti4_f16.c: New test.
+ * gcc.target/aarch64/sve2/acle/asm/luti4_f16_x2.c: New test.
+ * gcc.target/aarch64/sve2/acle/asm/luti4_s16.c: New test.
+ * gcc.target/aarch64/sve2/acle/asm/luti4_s16_x2.c: New test.
+ * gcc.target/aarch64/sve2/acle/asm/luti4_s8.c: New test.
+ * gcc.target/aarch64/sve2/acle/asm/luti4_u16.c: New test.
+ * gcc.target/aarch64/sve2/acle/asm/luti4_u16_x2.c: New test.
+ * gcc.target/aarch64/sve2/acle/asm/luti4_u8.c: New test.
+
+2025-01-21 Simon Martin <si...@nasilyan.com>
+
+ PR c++/118225
+ * g++.dg/cpp0x/constexpr-ice21.C: New test.
+
+2025-01-21 Tamar Christina <tamar.christ...@arm.com>
+
+ PR middle-end/118273
+ * gcc.target/aarch64/vect-simd-clone-4.c: New test.
+
+2025-01-21 Lulu Cheng <chengl...@loongson.cn>
+
+ * gcc.target/loongarch/arch-func-attr-1.c: Add '#pragma'.
+ * gcc.target/loongarch/cmodel-func-attr-1.c: Likewise.
+ * gcc.target/loongarch/lasx-func-attr-1.c: Likewise.
+ * gcc.target/loongarch/lsx-func-attr-1.c: Likewise.
+ * gcc.target/loongarch/strict_align-func-attr-1.c: Likewise.
+ * gcc.target/loongarch/strict_align-func-attr-2.c: Likewise.
+ * gcc.target/loongarch/vector-func-attr-1.c: Likewise.
+ * gcc.target/loongarch/arch-pragma-attr-1.c: Likewise.
+ * gcc.target/loongarch/cmodel-pragma-attr-1.c: New test.
+ * gcc.target/loongarch/lasx-pragma-attr-1.c: New test.
+ * gcc.target/loongarch/lasx-pragma-attr-2.c: New test.
+ * gcc.target/loongarch/lsx-pragma-attr-1.c: New test.
+ * gcc.target/loongarch/lsx-pragma-attr-2.c: New test.
+ * gcc.target/loongarch/strict_align-pragma-attr-1.c: New test.
+ * gcc.target/loongarch/strict_align-pragma-attr-2.c: New test.
+ * gcc.target/loongarch/vector-pragma-attr-1.c: New test.
+ * gcc.target/loongarch/pragma-push-pop.c: New test.
+
+2025-01-21 Lulu Cheng <chengl...@loongson.cn>
+
+ * gcc.target/loongarch/arch-func-attr-1.c: New test.
+ * gcc.target/loongarch/cmodel-func-attr-1.c: New test.
+ * gcc.target/loongarch/lasx-func-attr-1.c: New test.
+ * gcc.target/loongarch/lasx-func-attr-2.c: New test.
+ * gcc.target/loongarch/lsx-func-attr-1.c: New test.
+ * gcc.target/loongarch/lsx-func-attr-2.c: New test.
+ * gcc.target/loongarch/strict_align-func-attr-1.c: New test.
+ * gcc.target/loongarch/strict_align-func-attr-2.c: New test.
+ * gcc.target/loongarch/vector-func-attr-1.c: New test.
+ * gcc.target/loongarch/attr-check-error-message.c: New test.
+
+2025-01-21 Simon Martin <si...@nasilyan.com>
+
+ PR c++/118277
+ * g++.dg/cpp1z/constexpr-asm-5.C: Pass -fno-implicit-constexpr.
+
+2025-01-21 Alfie Richards <alfie.richa...@arm.com>
+
+ * g++.target/aarch64/mv-1.C: Add CLI flag.
+ * g++.target/aarch64/mv-symbols1.C: Add CLI flag.
+ * g++.target/aarch64/mv-symbols2.C: Add CLI flag.
+ * g++.target/aarch64/mv-symbols3.C: Add CLI flag.
+ * g++.target/aarch64/mv-symbols4.C: Add CLI flag.
+ * g++.target/aarch64/mv-symbols5.C: Add CLI flag.
+ * g++.target/aarch64/mv-warning1.C: New test.
+ * g++.target/aarch64/mvc-symbols1.C: Add CLI flag.
+ * g++.target/aarch64/mvc-symbols2.C: Add CLI flag.
+ * g++.target/aarch64/mvc-symbols3.C: Add CLI flag.
+ * g++.target/aarch64/mvc-symbols4.C: Add CLI flag.
+ * g++.target/aarch64/mv-pragma.C: Add CLI flag.
+ * g++.target/aarch64/mvc-warning1.C: New test.
+
+2025-01-21 Jakub Jelinek <ja...@redhat.com>
+
+ * c-c++-common/cpp/has-builtin-4.c: New test.
+
+2025-01-21 Jakub Jelinek <ja...@redhat.com>
+
+ PR c++/118532
+ * g++.dg/cpp/embed-22.C: New test.
+ * g++.dg/cpp/embed-23.C: New test.
+ * g++.dg/cpp0x/pr118532.C: New test.
+ * g++.dg/cpp2a/explicit20.C: New test.
+
2025-01-20 Nathaniel Shead <nathanielosh...@gmail.com>
* g++.dg/modules/export-6.C: Add structured binding tests.
diff --git a/libphobos/ChangeLog b/libphobos/ChangeLog
index 87b13b2ea000..97edc4a57833 100644
--- a/libphobos/ChangeLog
+++ b/libphobos/ChangeLog
@@ -1,3 +1,9 @@
+2025-01-21 Iain Buclaw <ibuc...@gdcproject.org>
+
+ PR d/118584
+ * libdruntime/config/mips/switchcontext.S: Add MIPS64 N64 ABI
+ implementation of fiber_switchContext.
+
2025-01-18 Iain Buclaw <ibuc...@gdcproject.org>
* libdruntime/MERGE: Merge upstream druntime d115713410.
