https://gcc.gnu.org/g:d5b3d9ed3447bd85c50d794421e97c757b84bfdf
commit r15-6096-gd5b3d9ed3447bd85c50d794421e97c757b84bfdf
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Wed Dec 11 00:19:28 2024 +0000
Daily bump.
Diff:
---
contrib/ChangeLog | 5 +
gcc/ChangeLog | 205 ++++++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/c-family/ChangeLog | 12 ++
gcc/cp/ChangeLog | 37 ++++++
gcc/m2/ChangeLog | 16 +++
gcc/testsuite/ChangeLog | 331 ++++++++++++++++++++++++++++++++++++++++++++++++
libgfortran/ChangeLog | 9 ++
libgomp/ChangeLog | 7 +
libstdc++-v3/ChangeLog | 99 +++++++++++++++
10 files changed, 722 insertions(+), 1 deletion(-)
diff --git a/contrib/ChangeLog b/contrib/ChangeLog
index 7768522f02a3..fea02d5f7fd5 100644
--- a/contrib/ChangeLog
+++ b/contrib/ChangeLog
@@ -1,3 +1,8 @@
+2024-12-10 David Malcolm <dmalc...@redhat.com>
+
+ * gcc-changelog/git_commit.py (bug_components): Add
+ 'libgdiagnostics' and 'sarif-replay'.
+
2024-12-09 Matthew Malcomson <mmalcom...@nvidia.com>
* clang-format: AlwaysBreakAfterReturnType set to
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4fc4b1fd2839..1e03dee99ffd 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,208 @@
+2024-12-10 David Malcolm <dmalc...@redhat.com>
+
+ PR other/117944
+ * libsarifreplay.cc (sarif_replayer::handle_result_obj): Get any
+ helpUri from the rule_obj and pass it to add_rule.
+
+2024-12-10 Vladimir N. Makarov <vmaka...@redhat.com>
+
+ PR rtl-optimization/117946
+ * lra-assigns.cc: (find_hard_regno_for_1): Use the biggest mode to
+ check ira_prohibited_class_mode_regs.
+
+2024-12-10 Marek Polacek <pola...@redhat.com>
+
+ PR c++/117880
+ * fold-const.cc (operand_compare::operand_equal_p) <case tcc_unary>:
+ Use OP_SAME_WITH_NULL instead of OP_SAME.
+
+2024-12-10 Wilco Dijkstra <wilco.dijks...@arm.com>
+
+ PR target/117675
+ * config/arm/arm.cc (arm_ldrd_legitimate_address): New function.
+ * config/arm/arm-protos.h (arm_ldrd_legitimate_address): New prototype.
+ * config/arm/constraints.md: Add new Uo constraint.
+ * config/arm/predicates.md (arm_ldrd_memory_operand): Add new predicate.
+ * config/arm/sync.md (arm_atomic_loaddi2_ldrd): Use
+ arm_ldrd_memory_operand and Uo.
+
+2024-12-10 Wilco Dijkstra <wilco.dijks...@arm.com>
+
+ * config/aarch64/aarch64-tuning-flags.def (AARCH64_EXTRA_TUNE_BASE):
New define.
+ * config/aarch64/tuning_models/ampere1b.h: Use AARCH64_EXTRA_TUNE_BASE.
+ * config/aarch64/tuning_models/cortexx925.h: Likewise.
+ * config/aarch64/tuning_models/fujitsu_monaka.h: Likewise.
+ * config/aarch64/tuning_models/generic_armv8_a.h: Likewise.
+ * config/aarch64/tuning_models/generic_armv9_a.h: Likewise.
+ * config/aarch64/tuning_models/neoversen1.h: Likewise.
+ * config/aarch64/tuning_models/neoversen2.h: Likewise.
+ * config/aarch64/tuning_models/neoversen3.h: Likewise.
+ * config/aarch64/tuning_models/neoversev1.h: Likewise.
+ * config/aarch64/tuning_models/neoversev2.h: Likewise.
+ * config/aarch64/tuning_models/neoversev3.h: Likewise.
+ * config/aarch64/tuning_models/neoversev3ae.h: Likewise.
+
+2024-12-10 Wilco Dijkstra <wilco.dijks...@arm.com>
+
+ * config/aarch64/aarch64.h (AARCH64_EXPAND_ALIGNMENT): Remove.
+ (DATA_ALIGNMENT): Use aarch64_data_alignment.
+ (LOCAL_ALIGNMENT): Use aarch64_stack_alignment.
+ * config/aarch64/aarch64.cc (aarch64_data_alignment): New function.
+ (aarch64_stack_alignment): Likewise.
+ * config/aarch64/aarch64-protos.h (aarch64_data_alignment): New
prototype.
+ (aarch64_stack_alignment): Likewise.
+
+2024-12-10 Wilco Dijkstra
<wdijk...@ip-10-252-53-150.eu-west-1.compute.internal>
+
+ * config/aarch64/aarch64.cc (aarch64_classify_address): Treat SIMD
structs
+ identically in little and bigendian.
+ * config/aarch64/aarch64-simd.md (aarch64_mov<mode>): Remove VSTRUCT
+ instructions.
+ (aarch64_be_mov<mode>): Allow little-endian, rename to
aarch64_mov<mode>.
+ (aarch64_be_movoi): Allow little-endian, rename to aarch64_movoi.
+ (aarch64_be_movci): Allow little-endian, rename to aarch64_movci.
+ (aarch64_be_movxi): Allow little-endian, rename to aarch64_movxi.
+ Remove big-endian special case in define_split variants.
+
+2024-12-10 Arsen Arsenović <ar...@aarsen.me>
+ Iain Sandoe <i...@sandoe.co.uk>
+
+ * dumpfile.cc (FIRST_ME_AUTO_NUMBERED_DUMP): Bump to 6 for sake
+ of the coroutine dump.
+
+2024-12-10 Richard Sandiford <richard.sandif...@arm.com>
+
+ * doc/md.texi (vcond@var{m}@var{n}, vcondu@var{m}@var{n})
+ (vcondeq@var{m}@var{n}): Delete.
+ (vcond_mask_@var{m}@var{n}): Redocument in standalone form.
+ * internal-fn.def (VCOND, VCONDU, VCONDEQ): Delete.
+ * internal-fn.cc (expand_vec_cond_optab_fn): Delete.
+ * optabs.def (vcond_optab, vcondu_optab, vcondeq_optab): Delete.
+
+2024-12-10 Richard Sandiford <richard.sandif...@arm.com>
+
+ * config/aarch64/aarch64-protos.h (aarch64_expand_sve_vcond): Delete.
+ * config/aarch64/aarch64-simd.md (<su><maxmin>v2di3): Expand into
+ separate vec_cmp and vcond_mask instructions, instead of using vcond.
+ (vcond<mode><mode>, vcond<v_cmp_mixed><mode>, vcondu<mode><mode>)
+ (vcondu<mode><v_cmp_mixed>): Delete.
+ * config/aarch64/aarch64-sve.md (vcond<SVE_ALL:mode><SVE_I:mode>)
+ (vcondu<SVE_ALL:mode><SVE_I:mode>, vcond<mode><v_fp_equiv>): Likewise.
+ * config/aarch64/aarch64.cc (aarch64_expand_sve_vcond): Likewise.
+ * config/aarch64/iterators.md (V_FP_EQUIV, v_fp_equiv, V_cmp_mixed)
+ (v_cmp_mixed): Likewise.
+
+2024-12-10 Saurabh Jha <saurabh....@arm.com>
+ Richard Sandiford <richard.sandif...@arm.com>
+
+ * config/aarch64/aarch64-builtins.cc
+ (aarch64_pragma_builtins_checker::require_immediate_lane_index): New
+ overload.
+ (aarch64_pragma_builtins_checker::check): Add support for FP8FMA
+ intrinsics.
+ (aarch64_expand_pragma_builtins): Likewise.
+ * config/aarch64/aarch64-c.cc
+ (aarch64_update_cpp_builtins): Conditionally define TARGET_FP8FMA.
+ * config/aarch64/aarch64-simd-pragma-builtins.def: Add the FP8FMA
+ intrinsics.
+ * config/aarch64/aarch64-simd.md:
+ (@aarch64_<FMLAL_FP8_HF:insn><mode): New pattern.
+ (@aarch64_<FMLAL_FP8_HF:insn>_lane<V8HF_ONLY:mode><VB:mode>):
+ Likewise.
+ (@aarch64_<FMLALL_FP8_SF:insn><mode): Likewise.
+ (@aarch64_<FMLALL_FP8_SF:insn>_lane<V8HF_ONLY:mode><VB:mode>):
+ Likewise.
+ * config/aarch64/iterators.md (V8HF_ONLY): New mode iterator.
+ (SVE2_FP8_TERNARY_VNX8HF): Rename to...
+ (FMLAL_FP8_HF): ...this.
+ (SVE2_FP8_TERNARY_LANE_VNX8HF): Delete in favor of FMLAL_FP8_HF.
+ (SVE2_FP8_TERNARY_VNX4SF): Rename to...
+ (FMLALL_FP8_SF): ...this.
+ (SVE2_FP8_TERNARY_LANE_VNX4SF): Delete in favor of FMLALL_FP8_SF.
+ (sve2_fp8_fma_op_vnx8hf, sve2_fp8_fma_op_vnx4sf): Fold into...
+ (insn): ...here.
+ * config/aarch64/aarch64-sve2.md: Update uses accordingly.
+
+2024-12-10 Saurabh Jha <saurabh....@arm.com>
+ Richard Sandiford <richard.sandif...@arm.com>
+
+ * config/aarch64/aarch64-builtins.cc
+ (enum class): Add ternary_lane.
+ (aarch64_fntype): Hnadle ternary_lane.
+ (aarch64_pragma_builtins_checker::require_immediate_lane_index): New
+ function.
+ (aarch64_pragma_builtins_checker::check): Handle the new intrinsics.
+ (aarch64_expand_pragma_builtin): Likewise.
+ * config/aarch64/aarch64-c.cc
+ (aarch64_update_cpp_builtins): Define TARGET_FP8DOT2 and
+ TARGET_FP8DOT4.
+ * config/aarch64/aarch64-simd-pragma-builtins.def: Define vdot
+ and vdot_lane intrinsics.
+ * config/aarch64/aarch64-simd.md
+ (@aarch64_<fpm_uns_op><mode>): New pattern.
+ (@aarch64_<fpm_uns_op>_lane<VQ_HSF_VDOT:mode><VB:mode>): Likewise.
+ * config/aarch64/iterators.md (VQ_HSF_VDOT): New mode iterator.
+ (UNSPEC_VDOT, UNSPEC_VDOT_LANE): New unspecs.
+ (fpm_uns_op): Handle them.
+ (VNARROWB, Vnbtype): New mode attributes.
+ (FPM_VDOT, FPM_VDOT_LANE): New int iterators.
+
+2024-12-10 Saurabh Jha <saurabh....@arm.com>
+ Richard Sandiford <richard.sandif...@arm.com>
+
+ * config/aarch64/aarch64-builtins.cc
+ (FLAG_USES_FPMR, FLAG_FP8): New flags.
+ (ENTRY): Modified to support ternary operations.
+ (enum class): New variants to support new signatures.
+ (struct aarch64_pragma_builtins_data): Extend types to 4 elements.
+ (aarch64_fntype): Handle new signatures.
+ (aarch64_get_low_unspec): New function.
+ (aarch64_convert_to_v64): New function, split out from...
+ (aarch64_expand_pragma_builtin): ...here. Handle new signatures.
+ * config/aarch64/aarch64-c.cc
+ (aarch64_update_cpp_builtins): New flag for FP8.
+ * config/aarch64/aarch64-simd-pragma-builtins.def: Define new fp8
+ intrinsics.
+ (ENTRY_BINARY, ENTRY_BINARY_LANE): Update for new ENTRY interface.
+ (ENTRY_UNARY, ENTRY_TERNARY, ENTRY_UNARY_FPM): New macros.
+ (ENTRY_BINARY_VHSDF_SIGNED): Likewise.
+ * config/aarch64/aarch64-simd.md
+ (@aarch64_<fpm_uns_op><mode>): New pattern.
+ (@aarch64_<fpm_uns_op><mode>_high): Likewise.
+ (@aarch64_<fpm_uns_op><mode>_high_be): Likewise.
+ (@aarch64_<fpm_uns_op><mode>_high_le): Likewise.
+ * config/aarch64/iterators.md (V4SF_ONLY, VQ_BHF): New mode iterators.
+ (UNSPEC_FCVTN_FP8, UNSPEC_FCVTN2_FP8, UNSPEC_F1CVTL_FP8)
+ (UNSPEC_F1CVTL2_FP8, UNSPEC_F2CVTL_FP8, UNSPEC_F2CVTL2_FP8)
+ (UNSPEC_FSCALE): New unspecs.
+ (VPACKB, VPACKBtype): New mode attributes.
+ (b): Add support for V[48][BH]F.
+ (FPM_UNARY_UNS, FPM_BINARY_UNS, SCALE_UNS): New int iterators.
+ (insn): New int attribute.
+
+2024-12-10 Richard Biener <rguent...@suse.de>
+
+ PR tree-optimization/117912
+ * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): For addresses
+ of zero-sized components do not set ->off if the object size pass
+ didn't run.
+ For OOB ARRAY_REF accesses in address expressions avoid setting
+ ->off if the object size pass didn't run.
+ (valueize_refs_1): Likewise.
+
+2024-12-10 Antoni Boucher <boua...@zoho.com>
+
+ PR target/117923
+ * config/aarch64/aarch64-builtins.cc: Remove GTY marker on
aarch64_simd_types,
+ aarch64_simd_types_trees (new variable), rename aarch64_simd_types to
+ aarch64_simd_types_trees.
+ * config/aarch64/aarch64-builtins.h: Remove GTY marker on
aarch64_simd_types,
+ aarch64_simd_types_trees (new variable).
+ * config/aarch64/aarch64-sve-builtins-shapes.cc: Rename
aarch64_simd_types to
+ aarch64_simd_types_trees.
+ * config/aarch64/aarch64-sve-builtins.cc: Rename aarch64_simd_types to
+ aarch64_simd_types_trees.
+
2024-12-09 Mariam Arutunian <mariamarutun...@gmail.com>
Richard Sandiford <richard.sandif...@arm.com>
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 61bea0399428..43fbb1840bff 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20241210
+20241211
diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
index 2e9131136488..33274b0a1317 100644
--- a/gcc/c-family/ChangeLog
+++ b/gcc/c-family/ChangeLog
@@ -1,3 +1,15 @@
+2024-12-10 Arsen Arsenović <ar...@aarsen.me>
+ Iain Sandoe <i...@sandoe.co.uk>
+
+ * c-pretty-print.cc (c_pretty_printer::storage_class_specifier):
+ Check that we're looking at a PARM_DECL or VAR_DECL before
+ looking at DECL_REGISTER.
+
+2024-12-10 Marek Polacek <pola...@redhat.com>
+
+ PR c++/117788
+ * c-warn.cc (do_warn_array_compare): Emit a permerror in C++26.
+
2024-12-09 Matthew Malcomson <mmalcom...@nvidia.com>
* c-common.cc (builtin_function_validate_nargs,
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 6407eabc95bc..74343fbc8b32 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,40 @@
+2024-12-10 Arsen Arsenović <ar...@aarsen.me>
+ Iain Sandoe <i...@sandoe.co.uk>
+
+ * coroutines.cc (dump_record_fields): New helper. Iterates a
+ RECORD_TYPEs TYPE_FIELDS and pretty-prints them.
+ (dmp_str): New. The lang-coro dump stream.
+ (coro_dump_id): New. ID of the lang-coro dump.
+ (coro_dump_flags): New. Flags passed to the lang-coro dump.
+ (coro_maybe_dump_initial_function): New helper. Prints, if
+ dumping is enabled, the fndecl passed to it as the original
+ function.
+ (coro_maybe_dump_ramp): New. Prints the ramp function passed to
+ it, if dumping is enabled.
+ (coro_maybe_dump_transformed_functions): New.
+ (cp_coroutine_transform::apply_transforms): Initialize the
+ lang-coro dump. Call coro_maybe_dump_initial_function on the
+ original function, as well as coro_maybe_dump_ramp, after the
+ transformation into the ramp is finished.
+ (cp_coroutine_transform::finish_transforms): Call
+ coro_maybe_dump_transformed_functions on the built actor and
+ destroy.
+ * cp-objcp-common.cc (cp_register_dumps): Register the coroutine
+ dump.
+ * cp-tree.h (coro_dump_id): Declare as extern.
+ * cxx-pretty-print.cc (pp_cxx_template_parameter): Don't call
+ TREE_TYPE on a TREE_LIST cell.
+ (cxx_pretty_printer::declaration): Handle FIELD_DECL similar to
+ VAR_DECL.
+
+2024-12-10 Marek Polacek <pola...@redhat.com>
+
+ PR c++/117788
+ * typeck.cc (cp_build_binary_op) <case EQ_EXPR>: Don't check
+ warn_array_compare. Check tf_warning_or_error instead of just
+ tf_warning. Maybe return an error_mark_node in C++26.
+ <case LE_EXPR>: Likewise.
+
2024-12-09 Marek Polacek <pola...@redhat.com>
Patrick Palka <ppa...@redhat.com>
diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog
index 086eb6e4c83f..dcdf222778fb 100644
--- a/gcc/m2/ChangeLog
+++ b/gcc/m2/ChangeLog
@@ -1,3 +1,19 @@
+2024-12-10 Gaius Mulley <gaiusm...@gmail.com>
+
+ PR modula2/117120
+ * gm2-compiler/M2CaseList.mod (CaseBoundsResolved): Rewrite.
+ (ConvertNulStr2NulChar): New procedure function.
+ (NulStr2NulChar): Ditto.
+ (GetCaseExpression): Ditto.
+ (OverlappingCaseBound): Rewrite.
+ * gm2-compiler/M2GCCDeclare.mod (CheckResolveSubrange): Allow
+ '' to be used as the subrange low limit.
+ * gm2-compiler/M2GenGCC.mod (FoldConvert): Rewrite.
+ (PopKindTree): Ditto.
+ (BuildHighFromString): Reformat.
+ * gm2-compiler/SymbolTable.mod (PushConstString): Add test for
+ length 0 and PushChar (nul).
+
2024-12-09 Gaius Mulley <gaiusm...@gmail.com>
PR modula2/115328
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index fd2ef28b340c..6cea931dd51b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,334 @@
+2024-12-10 Gaius Mulley <gaiusm...@gmail.com>
+
+ PR modula2/117120
+ * gm2/pim/pass/forloopnulchar.mod: New test.
+ * gm2/pim/pass/nulcharcase.mod: New test.
+ * gm2/pim/pass/nulcharvar.mod: New test.
+
+2024-12-10 Vladimir N. Makarov <vmaka...@redhat.com>
+
+ PR rtl-optimization/117946
+ * gcc.target/i386/pr117946.c: New.
+
+2024-12-10 Jerry DeLisle <jvdeli...@gcc.gnu.org>
+
+ PR fortran/117819
+ * gfortran.dg/pr117819.f90: New test.
+
+2024-12-10 Marek Polacek <pola...@redhat.com>
+
+ PR c++/117880
+ * g++.dg/warn/Wduplicated-branches8.C: New test.
+
+2024-12-10 Wilco Dijkstra <wilco.dijks...@arm.com>
+
+ PR target/117675
+ * gcc.target/arm/pr117675.c: Add new test.
+
+2024-12-10 Wilco Dijkstra
<wdijk...@ip-10-252-53-150.eu-west-1.compute.internal>
+
+ * gcc.target/aarch64/torture/simd-abi-8.c: Update to check for LDP/STP.
+
+2024-12-10 Marek Polacek <pola...@redhat.com>
+
+ PR c++/117788
+ * c-c++-common/Warray-compare-1.c: Expect an error in C++26.
+ * c-c++-common/Warray-compare-3.c: Likewise.
+ * c-c++-common/Warray-compare-4.c: New test.
+ * c-c++-common/Warray-compare-5.c: New test.
+ * g++.dg/warn/Warray-compare-1.C: New test.
+
+2024-12-10 Hans-Peter Nilsson <h...@axis.com>
+
+ * gcc.dg/tree-ssa/pr117973-1.c: New test.
+
+2024-12-10 Jonathan Wakely <jwak...@redhat.com>
+
+ * g++.dg/cpp0x/trivial1.C: Add -Wno-deprecated for C++26.
+
+2024-12-10 Maciej W. Rozycki <ma...@orcam.me.uk>
+
+ * gcc.c-torture/execute/memcpy-a1.c: Mark as expensive.
+ * gcc.c-torture/execute/memcpy-a2.c: Likewise.
+ * gcc.c-torture/execute/memcpy-a4.c: Likewise.
+ * gcc.c-torture/execute/memcpy-a8.c: Likewise.
+
+2024-12-10 Saurabh Jha <saurabh....@arm.com>
+ Richard Sandiford <richard.sandif...@arm.com>
+
+ * gcc.target/aarch64/pragma_cpp_predefs_4.c: Test TARGET_FP8FMA.
+ * gcc.target/aarch64/simd/vmla_fpm.c: New test.
+ * gcc.target/aarch64/simd/vmla_lane_indices_1.c: Likewise.
+
+2024-12-10 Saurabh Jha <saurabh....@arm.com>
+ Richard Sandiford <richard.sandif...@arm.com>
+
+ * gcc.target/aarch64/pragma_cpp_predefs_4.c: Test fp8dot2 and fp8dot4.
+ * gcc.target/aarch64/simd/vdot2_fpm.c: New test.
+ * gcc.target/aarch64/simd/vdot4_fpm.c: New test.
+ * gcc.target/aarch64/simd/vdot_lane_indices_1.c: New test.
+
+2024-12-10 Saurabh Jha <saurabh....@arm.com>
+ Richard Sandiford <richard.sandif...@arm.com>
+
+ * gcc.target/aarch64/acle/fp8.c: Remove check that fp8 feature
+ macro doesn't exist and...
+ * gcc.target/aarch64/pragma_cpp_predefs_4.c: ...test that it does here.
+ * gcc.target/aarch64/simd/scale_fpm.c: New test.
+ * gcc.target/aarch64/simd/vcvt_fpm.c: New test.
+
+2024-12-10 Richard Biener <rguent...@suse.de>
+
+ PR tree-optimization/117912
+ * c-c++-common/torture/pr117912-1.c: New testcase.
+ * c-c++-common/torture/pr117912-2.c: Likewise.
+ * c-c++-common/torture/pr117912-3.c: Likewise.
+
+2024-12-10 Hans-Peter Nilsson <h...@axis.com>
+
+ PR tree-optimization/117954
+ * gcc.dg/tree-ssa/pr111456-1.c: Pass
+ --param=logical-op-non-short-circuit=1.
+
+2024-12-10 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c: Take
+ tree-optimized pass for standard name check, and adjust the times.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c: Ditto.
+
+2024-12-10 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c: Take
+ tree-optimized pass for standard name check, and adjust the times.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c: Ditto.
+
+2024-12-10 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c: Take
+ tree-optimized pass for standard name check, and adjust the times.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c: Ditto.
+
+2024-12-10 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u16.c: Take
+ tree-optimized pass for standard name check, and adjust the times.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u8.c: Ditto.
+
+2024-12-10 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c: Take
+ tree-optimized pass for standard name check, and adjust the times.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c: Ditto.
+
+2024-12-10 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c: Take
+ tree-optimized pass for standard name check, and adjust the times.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c:
Ditto.
+ * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c:
Ditto.
+
2024-12-09 Mariam Arutunian <mariamarutun...@gmail.com>
* gcc.target/aarch64/crc-builtin-pmul64.c: New test.
diff --git a/libgfortran/ChangeLog b/libgfortran/ChangeLog
index 17e0caca26cf..2ebd0d7bc77b 100644
--- a/libgfortran/ChangeLog
+++ b/libgfortran/ChangeLog
@@ -1,3 +1,12 @@
+2024-12-10 Jerry DeLisle <jvdeli...@gcc.gnu.org>
+
+ PR fortran/117819
+ * io/read.c (read_decimal): If the read value is short of the
+ specified width and pad mode is PAD yes, check for BLANK ZERO
+ and adjust the value accordingly.
+ (read_decimal_unsigned): Likewise.
+ (read_radix): Likewise.
+
2024-12-04 Jerry DeLisle <jvdeli...@gcc.gnu.org>
PR fortran/117820
diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog
index acf2664a3952..cf9ed57ce800 100644
--- a/libgomp/ChangeLog
+++ b/libgomp/ChangeLog
@@ -1,3 +1,10 @@
+2024-12-10 Tobias Burnus <tbur...@baylibre.com>
+
+ * plugin/plugin-gcn.c (GOMP_OFFLOAD_dev2dev, GOMP_OFFLOAD_async_run):
+ Handle omp_async_queue == NULL after call to maybe_init_omp_async.
+ (GOMP_OFFLOAD_openacc_async_construct): Use error not fatal error,
+ partially reverting r15-5392.
+
2024-12-06 Thomas Schwinge <tschwi...@baylibre.com>
* testsuite/libgomp.c/declare-variant-3-sm89.c: New.
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index c50a760a1963..ff54960712c7 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,102 @@
+2024-12-10 Jonathan Wakely <jwak...@redhat.com>
+
+ * include/bits/memory_resource.h (polymoprhic_allocator): Use
+ feature test macro for P0339R6 features.
+
+2024-12-10 Marek Polacek <pola...@redhat.com>
+
+ PR c++/117788
+ * testsuite/std/ranges/adaptors/conditionally_borrowed.cc: Add a
+ FIXME, adjust.
+
+2024-12-10 Jonathan Wakely <jwak...@redhat.com>
+
+ * include/bits/stl_uninitialized.h (__is_bitwise_relocatable):
+ Revert to depending on is_trivial.
+
+2024-12-10 Giuseppe D'Angelo <giuseppe.dang...@kdab.com>
+
+ * include/std/type_traits: Deprecate is_trivial and
+ is_trivial_v.
+ * include/experimental/type_traits: Suppress the deprecation
+ warning.
+ * testsuite/20_util/is_trivial/requirements/explicit_instantiation.cc:
+ Amend the test to suppress the deprecation warning.
+ * testsuite/20_util/is_trivial/requirements/typedefs.cc:
+ Likewise.
+ * testsuite/20_util/is_trivial/value.cc: Likewise.
+ * testsuite/20_util/variable_templates_for_traits.cc: Likewise.
+ * testsuite/experimental/type_traits/value.cc: Likewise.
+ * testsuite/18_support/max_align_t/requirements/2.cc: Update the
+ test with P3247R2's new wording.
+
+2024-12-10 Giuseppe D'Angelo <giuseppe.dang...@kdab.com>
+
+ * testsuite/20_util/specialized_algorithms/uninitialized_copy/102064.cc:
+ Port away from is_trivial.
+ *
testsuite/20_util/specialized_algorithms/uninitialized_copy_n/102064.cc:
+ Likewise.
+ *
testsuite/20_util/specialized_algorithms/uninitialized_default/94540.cc:
+ Likewise.
+ *
testsuite/20_util/specialized_algorithms/uninitialized_default_n/94540.cc:
+ Likewise.
+ * testsuite/20_util/specialized_algorithms/uninitialized_fill/102064.cc:
+ Likewise.
+ *
testsuite/20_util/specialized_algorithms/uninitialized_fill_n/102064.cc:
+ Likewise.
+ *
testsuite/20_util/specialized_algorithms/uninitialized_value_construct/94540.cc:
+ Likewise.
+ *
testsuite/20_util/specialized_algorithms/uninitialized_value_construct_n/94540.cc:
+ Likewise.
+ * testsuite/23_containers/vector/cons/94540.cc: Likewise.
+ * testsuite/25_algorithms/copy/move_iterators/69478.cc:
+ Likewise.
+ * testsuite/25_algorithms/copy_backward/move_iterators/69478.cc:
+ Likewise.
+ * testsuite/25_algorithms/move/69478.cc: Likewise.
+ * testsuite/25_algorithms/move_backward/69478.cc: Likewise.
+ * testsuite/25_algorithms/rotate/constrained.cc: Likewise.
+ * testsuite/25_algorithms/rotate_copy/constrained.cc: Likewise.
+
+2024-12-10 Giuseppe D'Angelo <giuseppe.dang...@kdab.com>
+
+ * include/bits/ranges_uninitialized.h: port some if
+ constexpr away from is_trivial, and towards more specific
+ detections instead.
+
+2024-12-10 Giuseppe D'Angelo <giuseppe.dang...@kdab.com>
+
+ * include/bits/stl_uninitialized.h: Amended the
+ __is_bitwise_relocatable type trait.
+
+2024-12-10 Giuseppe D'Angelo <giuseppe.dang...@kdab.com>
+
+ * include/pstl/algorithm_impl.h (__remove_elements): Port away
+ from is_trivial.
+ (__pattern_inplace_merge): Likewise.
+ * include/pstl/glue_memory_impl.h (uninitialized_copy): Likewise.
+ (uninitialized_copy_n): Likewise.
+ (uninitialized_move): Likewise.
+ (uninitialized_move_n): Likewise.
+ (uninitialized_default_construct): Likewise.
+ (uninitialized_default_construct_n): Likewise.
+ (uninitialized_value_construct): Likewise.
+ (uninitialized_value_construct_n): Likewise.
+ *
testsuite/20_util/specialized_algorithms/pstl/uninitialized_construct.cc:
+ Likewise.
+ *
testsuite/20_util/specialized_algorithms/pstl/uninitialized_copy_move.cc:
+ Likewise.
+ *
testsuite/20_util/specialized_algorithms/pstl/uninitialized_fill_destroy.cc:
+ Likewise.
+ * testsuite/25_algorithms/pstl/alg_modifying_operations/partition.cc:
+ Likewise.
+
+2024-12-10 Giuseppe D'Angelo <giuseppe.dang...@kdab.com>
+
+ * include/bits/basic_string.h: Add a static_assert on the
+ char-like type.
+ * include/std/string_view: Port away from is_trivial.
+
2024-12-09 Jonathan Wakely <jwak...@redhat.com>
PR libstdc++/102259
