https://gcc.gnu.org/g:52cc5f0436314ab96130610af20fc3119f7d1451
commit r15-4533-g52cc5f0436314ab96130610af20fc3119f7d1451
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Tue Oct 22 00:20:27 2024 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 97 ++++++++++++
gcc/DATESTAMP | 2 +-
gcc/testsuite/ChangeLog | 396 ++++++++++++++++++++++++++++++++++++++++++++++++
libstdc++-v3/ChangeLog | 18 +++
4 files changed, 512 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6c55b4e77030..b77da017ed11 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,100 @@
+2024-10-21 Jeff Law <j...@ventanamicro.com>
+
+ PR rtl-optimization/116488
+ PR rtl-optimization/116579
+ PR rtl-optimization/116915
+ PR rtl-optimization/117226
+ * ext-dce.cc (carry_backpropagate): Properly handle SIGN_EXTEND, add
+ ZERO_EXTEND handling as well.
+ (ext_dce_process_uses): Call carry_backpropagate before the optimization
+ step.
+
+2024-10-21 Pan Li <pan2...@intel.com>
+
+ * config/riscv/autovec.md (sstrunc<mode><v_double_trunc>2): Add
+ new pattern sstrunc for double trunc.
+ (sstrunc<mode><v_quad_trunc>2): Ditto but for quad trunc.
+ (sstrunc<mode><v_oct_trunc>2): Ditto but for oct trunc.
+ * config/riscv/riscv-protos.h (expand_vec_double_sstrunc): Add
+ new func decl to expand double trunc.
+ (expand_vec_quad_sstrunc): Ditto but for quad trunc.
+ (expand_vec_oct_sstrunc): Ditto but for oct trunc.
+ * config/riscv/riscv-v.cc (expand_vec_double_sstrunc): Add new
+ func to expand double trunc.
+ (expand_vec_quad_sstrunc): Ditto but for quad trunc.
+ (expand_vec_oct_sstrunc): Ditto but for oct trunc.
+
+2024-10-21 Pan Li <pan2...@intel.com>
+
+ * tree-vect-patterns.cc (gimple_signed_integer_sat_trunc): Add
+ new func decl for signed SAT_TRUNC.
+ (vect_recog_sat_trunc_pattern): Try signed match pattern for
+ the SAT_TRUNC.
+
+2024-10-21 Pan Li <pan2...@intel.com>
+
+ * match.pd: Refine matching for vector signed SAT_TRUNC form 1.
+
+2024-10-21 Andrew Carlotti <andrew.carlo...@arm.com>
+
+ * config/aarch64/aarch64.cc (aarch64_register_move_cost):
+ Increase costs involving MOVEABLE_SYSREGS.
+
+2024-10-21 Andrew Stubbs <a...@baylibre.com>
+
+ * config/gcn/gcn.h (SGPR_REGNO_P): Silence warning.
+
+2024-10-21 Alex Coplan <alex.cop...@arm.com>
+
+ PR rtl-optimization/116783
+ * pair-fusion.cc (def_walker::cand_addr_uses): New.
+ (def_walker::def_walker): Add parameter for candidate address
+ uses.
+ (def_walker::alias_conflict_p): Declare.
+ (def_walker::addr_reg_conflict_p): New.
+ (def_walker::conflict_p): New.
+ (store_walker::store_walker): Add parameter for candidate
+ address uses and pass to base ctor.
+ (store_walker::conflict_p): Rename to ...
+ (store_walker::alias_conflict_p): ... this.
+ (load_walker::load_walker): Add parameter for candidate
+ address uses and pass to base ctor.
+ (load_walker::conflict_p): Rename to ...
+ (load_walker::alias_conflict_p): ... this.
+ (pair_fusion_bb_info::try_fuse_pair): Collect address register
+ uses for candidate insns and pass down to alias walkers.
+
+2024-10-21 Jeevitha <jeevi...@linux.ibm.com>
+
+ * config/rs6000/amo.h (enum _AMO_LD): Correct the function code for
+ _AMO_LD_DEC_BOUNDED.
+
+2024-10-21 Haochen Jiang <haochen.ji...@intel.com>
+
+ * common/config/i386/cpuinfo.h (get_intel_cpu): Refactor the
+ function for future expansion on different family.
+
+2024-10-21 liuhongt <hongtao....@intel.com>
+
+ PR target/117159
+ * config/i386/sse.md
+ (*<avx512>_cmp<V48H_AVX512VL:mode>3_zero_extend<SWI248x:mode>):
+ Change from define_insn_and_split to define_insn.
+ (*<avx512>_cmp<VI12_AVX512VL:mode>3_zero_extend<SWI248x:mode>):
+ Ditto.
+ (*<avx512>_ucmp<VI12_AVX512VL:mode>3_zero_extend<SWI248x:mode>):
+ Ditto.
+ (*<avx512>_ucmp<VI48_AVX512VL:mode>3_zero_extend<SWI248x:mode>):
+ Ditto.
+ (*<avx512>_cmp<V48H_AVX512VL:mode>3_zero_extend<SWI248x:mode>_2):
+ Split to the zero_extend pattern.
+ (*<avx512>_cmp<VI12_AVX512VL:mode>3_zero_extend<SWI248x:mode>_2):
+ Ditto.
+ (*<avx512>_ucmp<VI12_AVX512VL:mode>3_zero_extend<SWI248x:mode>_2):
+ Ditto.
+ (*<avx512>_ucmp<VI48_AVX512VL:mode>3_zero_extend<SWI248x:mode>_2):
+ Ditto.
+
2024-10-20 Jeff Law <j...@ventanamicro.com>
Revert:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 18b2d489abc8..cf7fc14e4eae 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20241021
+20241022
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ebaa2900cf59..f3780d4ac072 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,399 @@
+2024-10-21 Jeff Law <j...@ventanamicro.com>
+
+ PR rtl-optimization/116488
+ PR rtl-optimization/116579
+ PR rtl-optimization/116915
+ PR rtl-optimization/117226
+ * gcc.dg/torture/pr116488.c: New test.
+ * gcc.dg/torture/pr116579.c: New test.
+ * gcc.dg/torture/pr116915.c: New test.
+ * gcc.dg/torture/pr117226.c: New test.
+
+2024-10-21 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i16-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i32-to-i16.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i32-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i16.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i32.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-8-i64-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i16-to-i8.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i32-to-i16.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i32-to-i8.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i16.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i32.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-8-i64-to-i8.c:
New test.
+
+2024-10-21 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i16-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i32-to-i16.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i32-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i16.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i32.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-7-i64-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i16-to-i8.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i32-to-i16.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i32-to-i8.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i16.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i32.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-7-i64-to-i8.c:
New test.
+
+2024-10-21 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i16-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i16.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i16.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i32.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i16-to-i8.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i16.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i8.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i16.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i32.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i8.c:
New test.
+
+2024-10-21 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i16-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i32-to-i16.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i32-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i16.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i32.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-5-i64-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i16-to-i8.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i32-to-i16.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i32-to-i8.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i16.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i32.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-5-i64-to-i8.c:
New test.
+
+2024-10-21 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i16-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i32-to-i16.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i32-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i16.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i32.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-4-i64-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i16-to-i8.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i32-to-i16.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i32-to-i8.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i16.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i32.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-4-i64-to-i8.c:
New test.
+
+2024-10-21 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i16-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i16.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i32-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i16.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i32.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-3-i64-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i16-to-i8.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i16.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i32-to-i8.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i16.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i32.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-3-i64-to-i8.c:
New test.
+
+2024-10-21 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i16-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i32-to-i16.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i32-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i16.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i32.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-2-i64-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i16-to-i8.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i32-to-i16.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i32-to-i8.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i16.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i32.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-2-i64-to-i8.c:
New test.
+
+2024-10-21 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_data.h: Add test data for
+ signed SAT_TRUNC.
+ * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i16-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i32-to-i16.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i32-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i16.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i32.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-1-i64-to-i8.c: New
test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i16-to-i8.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i32-to-i16.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i32-to-i8.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i16.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i32.c:
New test.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-1-i64-to-i8.c:
New test.
+
+2024-10-21 Alex Coplan <alex.cop...@arm.com>
+
+ PR rtl-optimization/116783
+ * g++.dg/torture/pr116783.C: New test.
+
+2024-10-21 xuli <xu...@eswincomputing.com>
+
+ * gcc.target/riscv/sat_s_add-1.c: Skip flag -flto.
+ * gcc.target/riscv/sat_s_add-10.c: Ditto.
+ * gcc.target/riscv/sat_s_add-11.c: Ditto.
+ * gcc.target/riscv/sat_s_add-12.c: Ditto.
+ * gcc.target/riscv/sat_s_add-13.c: Ditto.
+ * gcc.target/riscv/sat_s_add-14.c: Ditto.
+ * gcc.target/riscv/sat_s_add-15.c: Ditto.
+ * gcc.target/riscv/sat_s_add-16.c: Ditto.
+ * gcc.target/riscv/sat_s_add-2.c: Ditto.
+ * gcc.target/riscv/sat_s_add-3.c: Ditto.
+ * gcc.target/riscv/sat_s_add-4.c: Ditto.
+ * gcc.target/riscv/sat_s_add-5.c: Ditto.
+ * gcc.target/riscv/sat_s_add-6.c: Ditto.
+ * gcc.target/riscv/sat_s_add-7.c: Ditto.
+ * gcc.target/riscv/sat_s_add-8.c: Ditto.
+ * gcc.target/riscv/sat_s_add-9.c: Ditto.
+ * gcc.target/riscv/sat_s_sub-1-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_sub-1-i32.c: Ditto.
+ * gcc.target/riscv/sat_s_sub-1-i64.c: Ditto.
+ * gcc.target/riscv/sat_s_sub-1-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_sub-2-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_sub-2-i32.c: Ditto.
+ * gcc.target/riscv/sat_s_sub-2-i64.c: Ditto.
+ * gcc.target/riscv/sat_s_sub-2-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_sub-3-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_sub-3-i32.c: Ditto.
+ * gcc.target/riscv/sat_s_sub-3-i64.c: Ditto.
+ * gcc.target/riscv/sat_s_sub-3-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_sub-4-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_sub-4-i32.c: Ditto.
+ * gcc.target/riscv/sat_s_sub-4-i64.c: Ditto.
+ * gcc.target/riscv/sat_s_sub-4-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-1-i16-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-1-i32-to-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-1-i32-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-1-i64-to-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-1-i64-to-i32.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-1-i64-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-2-i16-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-2-i32-to-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-2-i32-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-2-i64-to-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-2-i64-to-i32.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-2-i64-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-3-i16-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-3-i32-to-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-3-i32-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-3-i64-to-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-3-i64-to-i32.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-3-i64-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-4-i16-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-4-i32-to-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-4-i32-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-4-i64-to-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-4-i64-to-i32.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-4-i64-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-5-i16-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-5-i32-to-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-5-i32-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-5-i64-to-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-5-i64-to-i32.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-5-i64-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-6-i16-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-6-i32-to-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-6-i32-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-6-i64-to-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-6-i64-to-i32.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-6-i64-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-7-i16-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-7-i32-to-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-7-i32-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-7-i64-to-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-7-i64-to-i32.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-7-i64-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-8-i16-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-8-i32-to-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-8-i32-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-8-i64-to-i16.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-8-i64-to-i32.c: Ditto.
+ * gcc.target/riscv/sat_s_trunc-8-i64-to-i8.c: Ditto.
+ * gcc.target/riscv/sat_u_add-1.c: Ditto.
+ * gcc.target/riscv/sat_u_add-10.c: Ditto.
+ * gcc.target/riscv/sat_u_add-11.c: Ditto.
+ * gcc.target/riscv/sat_u_add-12.c: Ditto.
+ * gcc.target/riscv/sat_u_add-13.c: Ditto.
+ * gcc.target/riscv/sat_u_add-14.c: Ditto.
+ * gcc.target/riscv/sat_u_add-15.c: Ditto.
+ * gcc.target/riscv/sat_u_add-16.c: Ditto.
+ * gcc.target/riscv/sat_u_add-17.c: Ditto.
+ * gcc.target/riscv/sat_u_add-18.c: Ditto.
+ * gcc.target/riscv/sat_u_add-19.c: Ditto.
+ * gcc.target/riscv/sat_u_add-2.c: Ditto.
+ * gcc.target/riscv/sat_u_add-20.c: Ditto.
+ * gcc.target/riscv/sat_u_add-21.c: Ditto.
+ * gcc.target/riscv/sat_u_add-22.c: Ditto.
+ * gcc.target/riscv/sat_u_add-23.c: Ditto.
+ * gcc.target/riscv/sat_u_add-24.c: Ditto.
+ * gcc.target/riscv/sat_u_add-3.c: Ditto.
+ * gcc.target/riscv/sat_u_add-4.c: Ditto.
+ * gcc.target/riscv/sat_u_add-5.c: Ditto.
+ * gcc.target/riscv/sat_u_add-6.c: Ditto.
+ * gcc.target/riscv/sat_u_add-7.c: Ditto.
+ * gcc.target/riscv/sat_u_add-8.c: Ditto.
+ * gcc.target/riscv/sat_u_add-9.c: Ditto.
+ * gcc.target/riscv/sat_u_add_imm-1.c: Ditto.
+ * gcc.target/riscv/sat_u_add_imm-10.c: Ditto.
+ * gcc.target/riscv/sat_u_add_imm-11.c: Ditto.
+ * gcc.target/riscv/sat_u_add_imm-12.c: Ditto.
+ * gcc.target/riscv/sat_u_add_imm-13.c: Ditto.
+ * gcc.target/riscv/sat_u_add_imm-14.c: Ditto.
+ * gcc.target/riscv/sat_u_add_imm-15.c: Ditto.
+ * gcc.target/riscv/sat_u_add_imm-16.c: Ditto.
+ * gcc.target/riscv/sat_u_add_imm-2.c: Ditto.
+ * gcc.target/riscv/sat_u_add_imm-3.c: Ditto.
+ * gcc.target/riscv/sat_u_add_imm-4.c: Ditto.
+ * gcc.target/riscv/sat_u_add_imm-5.c: Ditto.
+ * gcc.target/riscv/sat_u_add_imm-6.c: Ditto.
+ * gcc.target/riscv/sat_u_add_imm-7.c: Ditto.
+ * gcc.target/riscv/sat_u_add_imm-8.c: Ditto.
+ * gcc.target/riscv/sat_u_add_imm-9.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-1.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-10.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-11.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-12.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-13.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-14.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-15.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-16.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-17.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-18.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-19.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-2.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-20.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-21.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-22.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-23.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-24.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-25.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-26.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-27.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-28.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-29.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-3.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-30.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-31.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-32.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-33.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-34.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-35.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-36.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-37.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-38.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-39.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-4.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-40.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-41.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-42.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-43.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-44.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-45.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-46.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-47.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-48.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-5.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-6.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-7.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-8.c: Ditto.
+ * gcc.target/riscv/sat_u_sub-9.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-1.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-10.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-10_1.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-10_2.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-11.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-11_1.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-11_2.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-12.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-13.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-13_1.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-13_2.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-14.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-14_1.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-14_2.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-15.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-15_1.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-15_2.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-16.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-1_1.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-1_2.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-2.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-2_1.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-2_2.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-3.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-3_1.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-3_2.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-4.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-5.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-5_1.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-5_2.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-6.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-6_1.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-6_2.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-7.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-7_1.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-7_2.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-8.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-9.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-9_1.c: Ditto.
+ * gcc.target/riscv/sat_u_sub_imm-9_2.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-1.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-10.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-11.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-12.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-13.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-14.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-15.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-16.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-17.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-18.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-19.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-2.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-20.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-21.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-22.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-23.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-24.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-3.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-4.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-5.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-6.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-7.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-8.c: Ditto.
+ * gcc.target/riscv/sat_u_trunc-9.c: Ditto.
+
+2024-10-21 Alexandre Oliva <ol...@adacore.com>
+
+ * gcc.target/arm/bti-1.c: Require arch, use its opts, drop skip.
+ * gcc.target/arm/bti-2.c: Likewise.
+ * gcc.target/arm/acle/pacbti-m-predef-11.c: Likewise.
+ * gcc.target/arm/acle/pacbti-m-predef-12.c: Likewise.
+ * gcc.target/arm/acle/pacbti-m-predef-7.c: Likewise.
+ * g++.target/arm/pac-1.C: Likewise. Drop +mve.
+
+2024-10-21 liuhongt <hongtao....@intel.com>
+
+ * gcc.target/i386/pr117159.c: New test.
+ * gcc.target/i386/avx512bw-pr103750-1.c: Remove xfail.
+ * gcc.target/i386/avx512bw-pr103750-2.c: Remove xfail.
+
2024-10-20 Jeff Law <j...@ventanamicro.com>
Revert:
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 62ddb03ab2db..bc199a0d409f 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,21 @@
+2024-10-21 Jonathan Wakely <jwak...@redhat.com>
+
+ * testsuite/26_numerics/headers/cmath/types_std_c++0x_neg.cc:
+ Move to ...
+ * testsuite/26_numerics/headers/cmath/specfun_c++17.cc: here and
+ adjust test to be valid for all -std dialects.
+
+2024-10-21 Jonathan Wakely <jwak...@redhat.com>
+
+ * include/bits/stl_vector.h (vector::_M_data_ptr): Remove
+ non-const overloads. Always return non-const pointer.
+
+2024-10-21 Jonathan Wakely <jwak...@redhat.com>
+
+ PR libstdc++/117220
+ * include/bits/stl_iterator.h: Move _GLIBCXX_NODISCARD
+ annotations after __attribute__((__always_inline__)).
+
2024-10-18 Jonathan Wakely <jwak...@redhat.com>
* include/bits/ranges_algobase.h (ranges::__assign_one): Remove.
