https://gcc.gnu.org/g:0ceb5cc1867fce940b2f4eaaa2b6ace49cb0b853

commit r15-4509-g0ceb5cc1867fce940b2f4eaaa2b6ace49cb0b853
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Mon Oct 21 00:17:11 2024 +0000

    Daily bump.

Diff:
---
 gcc/ChangeLog           |  9 +++++++++
 gcc/DATESTAMP           |  2 +-
 gcc/m2/ChangeLog        |  7 +++++++
 gcc/testsuite/ChangeLog | 10 ++++++++++
 4 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3c2a7b774e72..6c55b4e77030 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2024-10-20  Jeff Law  <j...@ventanamicro.com>
+
+       Revert:
+       2024-10-19  Craig Blackmore  <craig.blackm...@embecosm.com>
+
+       * config/riscv/riscv.cc (riscv_use_by_pieces_infrastructure_p):
+       New function.
+       (TARGET_USE_BY_PIECES_INFRASTRUCTURE_P): Define.
+
 2024-10-19  Andrew Pinski  <quic_apin...@quicinc.com>
 
        PR tree-optimization/112418
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f616e4b768b3..18b2d489abc8 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20241020
+20241021
diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog
index 7f775ea92c10..05b7d7c7e3a4 100644
--- a/gcc/m2/ChangeLog
+++ b/gcc/m2/ChangeLog
@@ -1,3 +1,10 @@
+2024-10-20  Gaius Mulley  <gaiusm...@gmail.com>
+
+       * gm2-compiler/M2MetaError.mod (op): Corrected ordering.
+       * gm2-compiler/P2SymBuild.def: Remove comment.
+       * gm2-compiler/P2SymBuild.mod (GetComparison): Replace
+       the word less with fewer.
+
 2024-10-19  Gaius Mulley  <gaiusm...@gmail.com>
 
        * gm2-compiler/M2MetaError.mod (op): Alphabetically order
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 658829c91dc8..ebaa2900cf59 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2024-10-20  Jeff Law  <j...@ventanamicro.com>
+
+       Revert:
+       2024-10-20  Craig Blackmore  <craig.blackm...@embecosm.com>
+
+       * gcc.target/riscv/rvv/autovec/pr113469.c: Expect mf2 setmem.
+       * gcc.target/riscv/rvv/base/setmem-2.c: Update f1 to expect
+       straight-line vector memset.
+       * gcc.target/riscv/rvv/base/setmem-3.c: Likewise.
+
 2024-10-19  Lewis Hyatt  <lhy...@gmail.com>
 
        PR preprocessor/114423

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