https://gcc.gnu.org/g:51486f081fbc1d7c09503f3341e5ff07a40480de
commit r15-3591-g51486f081fbc1d7c09503f3341e5ff07a40480de
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Thu Sep 12 00:17:03 2024 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 54 ++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/cp/ChangeLog | 7 +++
gcc/fortran/ChangeLog | 6 +++
gcc/testsuite/ChangeLog | 130 ++++++++++++++++++++++++++++++++++++++++++++++++
libstdc++-v3/ChangeLog | 6 +++
6 files changed, 204 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index db0bfca96918..ec0821e52998 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,57 @@
+2024-09-11 Martin Jambor <mjam...@suse.cz>
+
+ * ipa-cp.cc (propagate_vr_across_jump_function): Use
+ ipa_vr_supported_type_p instead of explicit check for integral and
+ pointer types.
+
+2024-09-11 Martin Jambor <mjam...@suse.cz>
+
+ * ipa-cp.h (ipa_supports_p): Rename to ipa_vr_supported_type_p.
+ * ipa-cp.cc (ipa_vr_operation_and_type_effects): Adjust called
+ function name.
+ (propagate_vr_across_jump_function): Likewise.
+ * ipa-prop.cc (ipa_compute_jump_functions_for_edge): Likewise.
+ (ipcp_get_parm_bits): Likewise.
+
+2024-09-11 Richard Earnshaw <rearn...@arm.com>
+
+ PR target/116597
+ * config/arm/arm.cc (arm_function_ok_for_sibcall): Use the list of
+ actuals for the call, not the list of formals.
+
+2024-09-11 Richard Biener <rguent...@suse.de>
+
+ PR tree-optimization/116674
+ * tree-vect-stmts.cc (vectorizable_simd_clone_call): Support
+ re-analysis.
+
+2024-09-11 Alex Coplan <alex.cop...@arm.com>
+
+ PR libstdc++/116140
+ * lto-streamer-in.cc (input_struct_function_base): Stream in
+ fn->has_unroll.
+ * lto-streamer-out.cc (output_struct_function_base): Stream out
+ fn->has_unroll.
+
+2024-09-11 Tobias Burnus <tbur...@baylibre.com>
+
+ * omp-general.cc (omp_runtime_api_procname): Add
+ omp_get_interop_{int,name,ptr,rc_desc,str,type_desc}
+ and omp_get_num_interop_properties.
+
+2024-09-11 Pan Li <pan2...@intel.com>
+
+ * match.pd: Add case 2 for the signed .SAT_ADD consumed by
+ vect pattern.
+ * tree-vect-patterns.cc (gimple_signed_integer_sat_add): Add new
+ matching func decl for signed .SAT_ADD.
+ (vect_recog_sat_add_pattern): Add signed .SAT_ADD pattern match.
+
+2024-09-11 liuhongt <hongtao....@intel.com>
+
+ * config/i386/x86-tune.def (X86_TUNE_FUSE_MOV_AND_ALU): Enable
+ for GNR and GNR-D.
+
2024-09-10 Prathamesh Kulkarni <prathame...@nvidia.com>
PR target/96265
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 2abf40291e63..8dcf10768ee4 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20240911
+20240912
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index c8bbe3a58f75..3f2e8ef479b4 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,10 @@
+2024-09-11 Alex Coplan <alex.cop...@arm.com>
+
+ PR libstdc++/116140
+ * semantics.cc (anotate_saver): New. Use it ...
+ (maybe_convert_cond): ... here, to ensure any ANNOTATE_EXPRs
+ remain the outermost expression(s) of the condition.
+
2024-09-10 Jakub Jelinek <ja...@redhat.com>
PR c++/116449
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 6e12d3b339e6..61e18b7ca709 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,9 @@
+2024-09-11 Tobias Burnus <tbur...@baylibre.com>
+
+ PR fortran/116661
+ * openmp.cc (gfc_match_omp_prefer_type): NULL init a gfc_expr
+ variable and use right locus in gfc_error.
+
2024-09-09 David Malcolm <dmalc...@redhat.com>
* cpp.cc (cb_cpp_diagnostic_cpp_option): Convert return type from
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 6fffbebb082e..7df4c42285d9 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,133 @@
+2024-09-11 Richard Earnshaw <rearn...@arm.com>
+
+ PR target/116597
+ * gcc.target/arm/pac-sibcall-2.c: New test.
+ * gcc.target/arm/pac-sibcall-3.c: New test.
+
+2024-09-11 Richard Biener <rguent...@suse.de>
+
+ PR tree-optimization/116674
+ * g++.dg/vect/pr116674.cc: New testcase.
+
+2024-09-11 Alex Coplan <alex.cop...@arm.com>
+
+ PR libstdc++/116140
+ * g++.dg/ext/pragma-unroll-lambda-lto.C: New test.
+
+2024-09-11 Alex Coplan <alex.cop...@arm.com>
+
+ PR libstdc++/116140
+ * lib/gcc-dg.exp (schedule-cleanups): Relax ltrans dumpfile
+ cleanup pattern to handle missing cases.
+
+2024-09-11 Alex Coplan <alex.cop...@arm.com>
+
+ PR libstdc++/116140
+ * g++.dg/ext/pragma-unroll-lambda.C: New test.
+
+2024-09-11 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Adjust
+ asm check and make it robust.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c: Ditto.
+
2024-09-10 Jakub Jelinek <ja...@redhat.com>
PR c++/116449
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 2540fd33bc6b..dcb20b02a8d4 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,9 @@
+2024-09-11 Alex Coplan <alex.cop...@arm.com>
+
+ PR libstdc++/116140
+ * include/bits/stl_algobase.h (std::__find_if): Add #pragma to
+ request GCC to unroll the loop.
+
2024-09-10 Jonathan Wakely <jwak...@redhat.com>
PR libstdc++/116159
