https://gcc.gnu.org/g:0555f6512991fc147b36f284c7a175c2b56de21b
commit r15-2976-g0555f6512991fc147b36f284c7a175c2b56de21b
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Sun Aug 18 00:17:44 2024 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 76 +++++++++++++++++++++++++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/testsuite/ChangeLog | 36 +++++++++++++++++++++++
libstdc++-v3/ChangeLog | 24 ++++++++++++++++
4 files changed, 137 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c26ae587e0e..b580e2594ff 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,79 @@
+2024-08-17 Jeff Law <j...@ventanamicro.com>
+
+ * ext-dce.cc (carry_backpropagate): Cast mask to HOST_WIDE_INT before
+ shifting.
+
+2024-08-17 Kevin Kirspel <kevin-kirs...@idexx.com>
+
+ * config/riscv/t-rtems: Add ilp32f multilib.
+
+2024-08-17 Jeff Law <j...@ventanamicro.com>
+
+ * config/v850/v850.md (rotlsi3): Allow more cases for V850E3V5+.
+
+2024-08-17 Jin Ma <ji...@linux.alibaba.com>
+
+ * config/riscv/vector.md: Allow scalar operand to be 0.
+
+2024-08-17 Jeff Law <j...@ventanamicro.com>
+
+ PR target/116282
+ * config/riscv/riscv-protos.h (riscv_const_insns): Add new argument.
+ * config/riscv/riscv.cc (riscv_build_integer): Add new argument
+ ALLOW_NEW_PSEUDOS. Pass it down to recursive calls and check it
+ before using synthesis which allows new registers to be created.
+ (riscv_split_integer_cost): Pass new argument to riscv_build_integer.
+ (riscv_integer_cost): Add ALLOW_NEW_PSEUDOS argument, pass it down to
+ riscv_build_integer.
+ (riscv_legitimate_constant_p): Pass new argument to riscv_const_insns.
+ (riscv_const_insns): New argment ALLOW_NEW_PSEUDOS. Pass it down to
+ riscv_integer_cost and riscv_const_insns.
+ (riscv_split_const_insns): Pass new argument to riscv_const_insns.
+ (riscv_move_integer, riscv_rtx_costs): Similarly.
+ * config/riscv/riscv.md (shadd with costly constant): Pass new argument
+ to riscv_const_insns.
+ * config/riscv/bitmanip.md (and with costly constant): Pass new argument
+ to riscv_const_insns.
+
+2024-08-17 Jin Ma <ji...@linux.alibaba.com>
+
+ * config/riscv/riscv-protos.h (riscv_vector_float_type_p): New.
+ * config/riscv/riscv-vector-builtins.cc
(function_instance::any_type_float_p):
+ Use riscv_vector_float_type_p instead of FLOAT_MODE_P for judgment.
+ * config/riscv/riscv.cc (riscv_vector_int_type_p): Change static to
extern.
+
+2024-08-17 Pan Li <pan2...@intel.com>
+
+ PR target/116280
+ * config/riscv/autovec-opt.md: Add quad truncation to
+ align the mode requirement for vwsll.
+
+2024-08-17 Feng Wang <wangf...@eswincomputing.com>
+
+ * config/riscv/autovec.md (v<bitmanip_optab><mode>3):
+ Add new define_expand pattern for vector rotate shift.
+
+2024-08-17 Gerald Pfeifer <ger...@pfeifer.com>
+
+ * doc/gm2.texi (What is GNU Modula-2): Tweak PIM4 link.
+
+2024-08-17 Gerald Pfeifer <ger...@pfeifer.com>
+
+ * doc/gm2.texi (Community): Tweak link to gm2 list archive.
+
+2024-08-17 Georg-Johann Lay <a...@gjlay.de>
+
+ PR target/116390
+ * config/avr/avr.cc (avr_out_movsi_mr_r_reg_disp_tiny): Fix
+ output templates for the reg_base == reg_src and
+ reg_src == reg_base - 2 cases.
+
+2024-08-17 曾治金 <zhijin.z...@spacemit.com>
+
+ PR target/116305
+ * config/riscv/riscv.cc (riscv_dwarf_poly_indeterminate_value): Take
+ BYTES_PER_RISCV_VECTOR for *factor instead of
riscv_bytes_per_vector_chunk.
+
2024-08-16 Mark Harmstone <m...@harmstone.com>
* dwarf2codeview.cc (enum cv_sym_type): Add S_REGREL32.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 720f32939ba..5e34934c797 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20240817
+20240818
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 9b9ee8cd97f..4a5bd9cb43e 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,39 @@
+2024-08-17 Jin Ma <ji...@linux.alibaba.com>
+
+ * gcc.target/riscv/rvv/base/bug-7.c: New test.
+ * gcc.target/riscv/rvv/base/bug-8.c: New test.
+
+2024-08-17 Jeff Law <j...@ventanamicro.com>
+
+ PR target/116282
+ * gcc.target/riscv/pr116282.c: New test.
+
+2024-08-17 Jin Ma <ji...@linux.alibaba.com>
+
+ * gcc.target/riscv/rvv/base/bug-9.c: New test.
+
+2024-08-17 Pan Li <pan2...@intel.com>
+
+ PR target/116280
+ * gcc.target/riscv/rvv/base/pr116280-1.c: New test.
+ * gcc.target/riscv/rvv/base/pr116280-2.c: New test.
+
+2024-08-17 Feng Wang <wangf...@eswincomputing.com>
+
+ * gcc.target/riscv/rvv/autovec/binop/vrolr-1.c: New test.
+ * gcc.target/riscv/rvv/autovec/binop/vrolr-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/binop/vrolr-template.h: New test.
+
+2024-08-17 Georg-Johann Lay <a...@gjlay.de>
+
+ PR target/116390
+ * gcc.target/avr/torture/pr116390.c: New test.
+
+2024-08-17 曾治金 <zhijin.z...@spacemit.com>
+
+ PR target/116305
+ * gcc.target/riscv/rvv/base/scalable_vector_cfi.c: New test.
+
2024-08-16 Torbjörn SVENSSON <torbjorn.svens...@foss.st.com>
* g++.dg/warn/pr33738.C: Added -fno-short-enums.
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 9311bfb3e83..d27a3ac6670 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,27 @@
+2024-08-17 Gerald Pfeifer <ger...@pfeifer.com>
+
+ * doc/xml/manual/abi.xml: Update reference to
+ gcc.gnu.org/onlinedocs.
+ * doc/xml/manual/concurrency_extensions.xml (interface): Ditto.
+ * doc/xml/manual/extensions.xml: Ditto.
+ * doc/xml/manual/parallel_mode.xml: Ditto.
+ * doc/xml/manual/shared_ptr.xml: Ditto.
+ * doc/xml/manual/using_exceptions.xml: Ditto. And change GNU GCC
+ to GCC.
+ * doc/html/manual/abi.html: Regenerate.
+ * doc/html/manual/ext_concurrency_impl.html: Ditto.
+ * doc/html/manual/ext_demangling.html: Ditto.
+ * doc/html/manual/memory.html: Ditto.
+ * doc/html/manual/parallel_mode_design.html: Ditto.
+ * doc/html/manual/parallel_mode_using.html: Ditto.
+ * doc/html/manual/using_exceptions.html: Ditto.
+
+2024-08-17 Gerald Pfeifer <ger...@pfeifer.com>
+
+ * doc/xml/manual/prerequisites.xml: Tweak two links to
+ installation docs. Fix grammar.
+ * doc/html/manual/setup.html: Regenerate.
+
2024-08-16 Hans-Peter Nilsson <h...@axis.com>
PR libstdc++/116362
