https://gcc.gnu.org/g:d1b25543f93c26a6f4b8dd366792bdd8fd9cf7a7
commit r15-2208-gd1b25543f93c26a6f4b8dd366792bdd8fd9cf7a7
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Tue Jul 23 00:19:00 2024 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 131 +++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/cp/ChangeLog | 13 +++
gcc/fortran/ChangeLog | 7 ++
gcc/testsuite/ChangeLog | 247 ++++++++++++++++++++++++++++++++++++++++++++++++
5 files changed, 399 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 61fc57be9492..353ce3b6e2a8 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,134 @@
+2024-07-22 Jan Hubicka <hubi...@ucw.cz>
+
+ PR ipa/109985
+ * ipa-modref.cc (modref_summary::useful_p): Fix handling of ECF_NOVOPS.
+ (modref_access_analysis::process_fnspec): Likevise.
+ (modref_access_analysis::analyze_call): Likevise.
+ (propagate_unknown_call): Likevise.
+ (modref_propagate_in_scc): Likevise.
+ (modref_propagate_flags_in_scc): Likewise.
+ (ipa_merge_modref_summary_after_inlining): Likewise.
+
+2024-07-22 Jan Hubicka <hubi...@ucw.cz>
+
+ PR ipa/111613
+ * ipa-modref.cc (analyze_parms): Do not preserve EAF_NO_DIRECT_READ and
+ EAF_NO_INDIRECT_READ from past flags.
+
+2024-07-22 Michael Meissner <meiss...@linux.ibm.com>
+
+ * config.gcc (powerpc*-*-*): Add support for power11.
+ * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11.
+ * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
+ * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
+ * config/rs6000/driver-rs6000.cc (asm_names): Likewise.
+ * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define.
+ * config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11.
+ * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+ _ARCH_PWR11 if -mcpu=power11.
+ * config/rs6000/rs6000-cpus.def (POWER11_MASKS_SERVER): New define.
+ (POWERPC_MASKS): Add power11.
+ (power11 cpu): Add power11 definition.
+ * config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11
processor.
+ * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
+ * config/rs6000/rs6000-tables.opt: Regenerate.
+ * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add power11
+ support.
+ (rs6000_machine_from_flags): Likewise.
+ (rs6000_reassociation_width): Likewise.
+ (rs6000_adjust_cost): Likewise.
+ (rs6000_issue_rate): Likewise.
+ (rs6000_sched_reorder): Likewise.
+ (rs6000_sched_reorder2): Likewise.
+ (rs6000_register_move_cost): Likewise.
+ (rs6000_opt_masks): Likewise.
+ * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
+ * config/rs6000/rs6000.md (cpu attribute): Add power11.
+ * config/rs6000/rs6000.opt (-mpower11): Add internal power11 flag.
+ * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=power11.
+ * config/rs6000/power10.md (all reservations): Add power11 support.
+
+2024-07-22 Jeff Law <j...@ventanamicro.com>
+
+ PR rtl-optimization/115877
+ * ext-dce.cc (ext_dce_process_sets): More correctly handle SUBREG
+ destinations.
+
+2024-07-22 Jan Hubicka <hubi...@ucw.cz>
+
+ PR ipa/115033
+ * ipa-modref.cc (modref_eaf_analysis::analyze_ssa_name): Fix checking of
+ EAF flags when analysing values dereferenced as function parameters.
+
+2024-07-22 Jan Hubicka <hubi...@ucw.cz>
+
+ PR ipa/114207
+ * ipa-prop.cc (unadjusted_ptr_and_unit_offset): Fix accounting of
offsets in ADDR_EXPR.
+
+2024-07-22 Jan Hubicka <hubi...@ucw.cz>
+
+ PR ipa/115277
+ * ipa-icf-gimple.cc (func_checker::compare_loops): compare loop
+ bounds.
+
+2024-07-22 Richard Sandiford <richard.sandif...@arm.com>
+
+ PR rtl-optimization/116009
+ * rtl-ssa/accesses.cc (function_info::add_def): Set the root
+ local variable after removing the old clobber group.
+
+2024-07-22 Richard Sandiford <richard.sandif...@arm.com>
+
+ * rtl-ssa/accesses.h (rtl_ssa::pp_def_splay_tree): Declare.
+ (dump, debug): Add overloads for def_splay_tree.
+ * rtl-ssa/accesses.cc (rtl_ssa::pp_def_splay_tree): New function.
+ (dump, debug): Add overloads for def_splay_tree.
+
+2024-07-22 Richard Sandiford <richard.sandif...@arm.com>
+
+ PR target/115969
+ * config/aarch64/aarch64.cc (aarch64_simd_mem_operand_p): Require
+ the operand to be a legitimate memory_operand.
+
+2024-07-22 Jeff Law <j...@ventanamicro.com>
+
+ PR rtl-optimization/115877
+ * ext-dce.cc (group_limit): New function.
+ (mark_reg_live): Likewise.
+ (ext_dce_process_sets): Use new functions.
+ (ext_dce_process_uses): Likewise.
+ (ext_dce_init): Likewise.
+
+2024-07-22 Richard Biener <rguent...@suse.de>
+
+ * fold-const.cc (operand_compare::hash_operand): Fix hash
+ of WIDEN_*_EXPR.
+
+2024-07-22 Richard Biener <rguent...@suse.de>
+
+ * inchash.h (inchash::end): Make const.
+ (inchash::merge): Take const reference hash argument.
+ (inchash::add_commutative): Likewise.
+
+2024-07-22 Tamar Christina <tamar.christ...@arm.com>
+
+ PR tree-optimization/115531
+ * config/aarch64/aarch64.cc
+ (aarch64_conditional_operation_is_expensive): New.
+ (TARGET_VECTORIZE_CONDITIONAL_OPERATION_IS_EXPENSIVE): New.
+
+2024-07-22 Tamar Christina <tamar.christ...@arm.com>
+
+ PR tree-optimization/115531
+ * tree-vect-patterns.cc (vect_cond_store_pattern_same_ref): New.
+ (vect_recog_cond_store_pattern): New.
+ (vect_vect_recog_func_ptrs): Use it.
+ * target.def (conditional_operation_is_expensive): New.
+ * doc/tm.texi: Regenerate.
+ * doc/tm.texi.in: Document it.
+ * targhooks.cc (default_conditional_operation_is_expensive): New.
+ * targhooks.h (default_conditional_operation_is_expensive): New.
+
2024-07-21 Jeff Law <j...@ventanamicro.com>
PR rtl-optimization/115877
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 01bbf6ed5e1f..833d506febb5 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20240722
+20240723
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index c9c242ecd3d9..22cf73316a47 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,16 @@
+2024-07-22 Jakub Jelinek <ja...@redhat.com>
+
+ * cp-tree.def (UNARY_LEFT_FOLD_EXPR): Use FOLD_EXPR_MODIFY_P instead
+ of FOLD_EXPR_MOD_P or FOLDEXPR_MOD_P in the comment. Comment
+ formatting fixes.
+ (ATOMIC_CONSTEXPR): Use CONSTR_INFO instead of ATOMIC_CONSTR_INFO
+ and ATOMIC_CONSTR_MAP instead of ATOMIC_CONSTR_PARMS in the comment.
+ Comment formatting fixes.
+ (CONJ_CONSTR): Remove comment about third operand. Use CONSTR_INFO
+ instead of CONJ_CONSTR_INFO and DISJ_CONSTR_INFO.
+ (CHECK_CONSTR): Use CHECK_CONSTR_ARGS instead of
+ CHECK_CONSTR_ARGUMENTS.
+
2024-07-20 Andi Kleen <a...@gcc.gnu.org>
Revert:
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 0940f731cd6a..08f8e4e7e196 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,10 @@
+2024-07-22 Andre Vehreschild <ve...@gcc.gnu.org>
+
+ PR fortran/88624
+ * trans-expr.cc (gfc_conv_procedure_call): Treat
+ pointers/references (e.g. from parameters) correctly by derefing
+ them.
+
2024-07-21 Paul Thomas <pa...@gcc.gnu.org>
PR fortran/59104
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ee66c12a6fa3..1f25760edf24 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,250 @@
+2024-07-22 Jan Hubicka <hubi...@ucw.cz>
+
+ PR ipa/111613
+ * gcc.c-torture/pr111613.c: New test.
+
+2024-07-22 Michael Meissner <meiss...@linux.ibm.com>
+
+ * gcc.target/powerpc/power11-1.c: New test.
+ * gcc.target/powerpc/power11-2.c: Likewise.
+ * gcc.target/powerpc/power11-3.c: Likewise.
+
+2024-07-22 Jan Hubicka <hubi...@ucw.cz>
+
+ PR ipa/115033
+ * gcc.c-torture/execute/pr115033.c: New test.
+
+2024-07-22 Jan Hubicka <hubi...@ucw.cz>
+
+ PR ipa/114207
+ * gcc.c-torture/execute/pr114207.c: New test.
+
+2024-07-22 Jan Hubicka <hubi...@ucw.cz>
+
+ * gcc.c-torture/compile/pr115277.c: New test.
+
+2024-07-22 Richard Sandiford <richard.sandif...@arm.com>
+
+ PR rtl-optimization/116009
+ * gcc.c-torture/compile/pr116009.c: New test.
+
+2024-07-22 Richard Sandiford <richard.sandif...@arm.com>
+
+ PR target/115969
+ * gcc.target/aarch64/pr115969.c: New test.
+
+2024-07-22 Andre Vehreschild <ve...@gcc.gnu.org>
+
+ PR fortran/88624
+ * gfortran.dg/coarray/dummy_1.f90: Add calling function trough
+ function.
+ * gfortran.dg/pr88624.f90: New test.
+
+2024-07-22 Tamar Christina <tamar.christ...@arm.com>
+
+ PR tree-optimization/115531
+ * gcc.dg/vect/vect-conditional_store_1.c: New test.
+ * gcc.dg/vect/vect-conditional_store_2.c: New test.
+ * gcc.dg/vect/vect-conditional_store_3.c: New test.
+ * gcc.dg/vect/vect-conditional_store_4.c: New test.
+
+2024-07-22 Sam James <s...@gentoo.org>
+
+ PR target/108699
+ * gcc.target/powerpc/pr108699.c: Fix 'dg-run' typo.
+
+2024-07-22 Pan Li <pan2...@intel.com>
+
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary.h: Move to...
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vvv_run.h: ...here.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_scalar.h: Move to...
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vvx_run.h: ...here.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h: Move to...
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx_run.h: ...here.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Adjust
+ the include file names.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-1.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-17.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-18.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-19.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-2.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-20.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-25.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-26.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-27.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-28.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-29.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-3.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-30.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-31.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-32.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-4.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-1.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-2.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-3.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-4.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-5.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-6.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-7.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-8.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-1.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-2.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-3.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-4.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-5.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-6.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-7.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-8.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-1.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-2.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-3.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c: Ditto
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Ditto
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Ditto
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Ditto
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c: Ditto
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c: Ditto
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c: Ditto
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-1.c: Ditto
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-2.c: Ditto
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-3.c: Ditto
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-4.c: Ditto
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-5.c: Ditto
+ * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-6.c: Ditto
+ * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Move to...
+ * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: ...here.
+
2024-07-21 Paul Thomas <pa...@gcc.gnu.org>
PR fortran/59104
