Hi, From origin insn seqs, I think the insn 'r500=unspec[r100] 300’ is in Good place because of the bypass of my pipeline description, it is not needed to schedule.
But the result of Sched1 pass schedule it, I check the souce code of sched-rgn.c & haifa-sched.c From compute_priorities() I think the dependence of insn consider dependence of register Or memory first, but do not include any cpu resource conflict with defined by ‘define_cpu_unit' Is there any way to control my case ? Or my description of pipeline is not good ? My gcc version is 8.1.0 insn seqs from Origin: r80=VAL r100=unspec[r80] 200 r81=VAL r101=unspec[r81] 200 r500=unspec[r100] 300 r82=VAL r102=unspec[r82] 200 r501=unspec[r101] 300 r502=unspec[r102] 300 ------------------------ My pipeline like as: (define_cpu_unit "ex1, ex2” "pipe_name") (define_cpu_unit “tx” "pipe_name") Insn unspec 200 as T1, latency is 12, use ex1,2 Insn unspec 300 as T2, latency is 12, use tx (define_bypass 0 “T1” "T2") ------------------------ insn seqs after Sched1: r80=VAL r81=VAL r82=VAL r100=unspec[r80] 200 r101=unspec[r81] 200 r102=unspec[r82] 200 r500=unspec[r100] 300 r501=unspec[r101] 300 r502=unspec[r102] 300 Jojo
