(Sorry, my mail program crashed... trying repost, correct now...)
I found this patch from 2003 by Tamas Gergely that was never merged for ARM. Though it seems to still be valid, since when applying it, the CSiBE benchmark reduce total code size -170 bytes, making 35 out of 893 files smaller (from -4 to -12 bytes (1-3 instructions). Could it be considered to apply it, since it abviously still is valid and reduce code size for ARM 32bit. The peephole2 pattern still is not matched. Bug Bug 9663<https://gcc.gnu.org/bugzilla/show_bug.cgi?id=9663> - [arm] gcc-20030127 misses an optimization opportunity https://gcc.gnu.org/bugzilla/show_bug.cgi?id=9663 Message https://gcc.gnu.org/ml/gcc-patches/2003-02/msg00204.html Adapted and updated patch from Tamas Gergely: diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 20bdc2bec37..4c924499ad9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2019-06-01 Fredrik Hederstierna <fred...@hederstierna.com> + Tamas Gergely <ger...@rgai.hu> + + * gcc/config/arm/arm.md: new peephole2 pattern added for extending + move and compare parallelization. Retake from 2003 patch adapted. + 2019-06-01 Martin Sebor <mse...@redhat.com> PR middle-end/90694 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index ae582172ab9..753d18fbfc5 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -10951,6 +10951,19 @@ "" ) +; The same as the previous, but with exchanged operands +; +(define_peephole2 + [(set (match_operand:SI 0 "arm_general_register_operand" "") + (match_operand:SI 1 "arm_general_register_operand" "")) + (set (reg:CC CC_REGNUM) + (compare:CC (match_dup 0) (const_int 0)))] + "TARGET_ARM" + [(parallel [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int 0))) + (set (match_dup 0) (match_dup 1))])] + "" +) + (define_split [(set (match_operand:SI 0 "s_register_operand" "") (and:SI (ge:SI (match_operand:SI 1 "s_register_operand" "")
