On Wed, 2018-05-16 at 17:30 +0100, Richard Earnshaw (lists) wrote: > On 16/05/18 17:21, Steve Ellcey wrote: > > > > It doesn't look like GCC has any existing mechanism for having different > > sets of caller saved/callee saved registers depending on the function > > attributes of the calling or called function. > > > > Changing what registers a callee function saves and restores shouldn't > > be too difficult since that can be done when generating the prologue > > and epilogue code but changing what registers a caller saves/restores > > when doing the call seems trickier. The macro > > TARGET_HARD_REGNO_CALL_PART_CLOBBERED doesn't know anything about the > > function being called. It returns true/false depending on just the > > register number and mode. > > > > Steve Ellcey > > sell...@cavium.com > > > > Actually, we can. See, for example, the attribute((pcs)) for the ARM > port. I think we could probably handle this automagically for the SVE > vector calling convention in AArch64. > > R.
Interesting, it looks like one could use aarch64_emit_call to emit extra use_reg / clobber_reg instructions but in this case we want to tell the caller that some registers are not being clobbered by the callee. The ARM port does not define TARGET_HARD_REGNO_CALL_PART_CLOBBERED and that seemed like one of the most problamatic issues with Aarch64. Maybe we would have to undefine this for aarch64 and use explicit clobbers to say what floating point registers / vector registers are clobbered for each call? I wonder how that would affect register allocation. Steve Ellcey sell...@cavium.com
