Re: Bit-field struct member sign extension pattern results in redundant

[Andrew Pinski]

On Thu, Aug 17, 2017 at 3:29 PM, Michael Clark <michaeljcl...@mac.com> wrote:
> Sorry I had to send again as my Apple mailer is munging emails. I’ve disabled 
> RTF.
>
>
> This one is quite interesting:
>
> - https://cx.rv8.io/g/WXWMTG
>
> It’s another target independent bug. x86 is using some LEA followed by SAR 
> trick with a 3 bit shift. Surely SHL 27, SAR 27 would suffice. In any case 
> RISC-V seems like a nice target to try to fix this codegen for, as its less 
> risk than attempting a fix in x86 ;-)
>
> - https://github.com/riscv/riscv-gcc/issues/89
>
> code:
>
>         template <typename T, unsigned B>
>         inline T signextend(const T x)
>         {
>         struct {T x:B;} s;
>         return s.x = x;
>         }
>
>         int sx5(int x) {
>                 return signextend<signed int,5>(x);
>         }

on AARCH64 I get:
        sbfiz   w0, w0, 3, 5
        asr     w0, w0, 3
        ret

Which is:
(insn 7 6 8 2 (set (reg:SI 80)
        (sign_extend:SI (ashift:QI (reg:QI 0 x0 [ x+3 ])
                (const_int 3 [0x3])))) t.cc:5 557 {*extendsi_ashlqi}
     (expr_list:REG_DEAD (reg:SI 0 x0 [ x ])
        (nil)))

(insn 14 9 17 2 (set (reg/i:SI 0 x0)
        (ashiftrt:SI (reg:SI 80)
            (const_int 3 [0x3]))) t.cc:10 530 {*aarch64_ashr_sisd_or_int_si3}
     (expr_list:REG_DEAD (reg:SI 80)
        (nil)))

What I suspect is we get a QImode register in there and that is what
is happening to both x86 and riscv.

Thanks,
Andrew

>
> riscv asm:
>
>         sx5(int):
>           slliw a0,a0,3
>           slliw a0,a0,24
>           sraiw a0,a0,24
>           sraiw a0,a0,3
>           ret
>
> hand coded riscv asm
>
>         sx5(int):
>           slliw a0,a0,27
>           sraiw a0,a0,27
>           ret
>
> x86 asm:
>
>         sx5(int):
>           lea eax, [0+rdi*8]
>           sar al, 3
>           movsx eax, al
>           ret
>
> hand coded x86 asm (no worse because the sar depends on the lea)
>
>         sx5(int):
>           shl edi, 27
>           sar edi, 27
>           movsx eax, dl
>           ret