On 03/15/2017 08:26 AM, Segher Boessenkool wrote:
Since SPE and VLE only share the part of the rs6000 port that doesn't
change at all (except for a bug fix once or twice a year), and everything
else needs special cases all over the place, it seems to me it would be
best for everyone if we split the rs6000 port in two, one for SPE and VLE
and one for the rest. Both ports could then be very significantly
simplified.
I am assuming SPE and VLE do not support AltiVec or 64-bit PowerPC,
please correct me if that is incorrect. Also, is "normal" floating
point supported at all?
Do you (AdaCore and Mentor) think splitting the port is a good idea?
I can't speak on behalf of Mentor, and Andrew is the target expert here,
but we currently do ship all of SPE, VLE, and AltiVec multilibs in the
same powerpc-eabi toolchain. Specifically, the list is
default (603e, e300c3, G2, etc)
-te500v1
-te500v2
-te500mc
-te600
-te200z0
-te200z3
-te200z4
plus some soft-float variants, etc. Splitting these up into multiple
toolchains that have to be statically configured for a particular
architecture wouldn't be zero-cost either for us, other groups in Mentor
that repackage our toolchains, or our end users.
I'm wondering whether the code in the rs6000 backend could be refactored
to better abstract and separate the complicated processor-dependent bits?
-Sandra
