On a machine with ABI ILP32LL64:
(insn 123 122 124 (nil) (set (reg:SI 392)
(mem:SI (plus:SI (reg/v:SI 386)
(reg/v:SI 349)) [0 sec 0 space 0, cmsmode 0 S4 A32])) -1 (nil)
(nil))
If we support legitimate memory addresses like [r1+r2] (e.g. indexed
addresses), can the above RTL match such a load? I am asking because
of overflows, I am not sure how that part is defined, and where the
Spec is. What do I need to check in the backend for such a definition?
Is this POINTER_SIZE? E.g. what if the machine supports > 32 bits, who
is responsible to make sure that there is no overflow > 32 bits in
this case? Compiler? Assembler? Or even the user?
Thanks,
Hendrik
