"Radu Hobincu" <radu.hobi...@arh.pub.ro> writes:
> However, now I have another problem. I have 2 instructions in the ISA:
> 'where' and 'endwhere' which modify the behavior of the instructions put
> in between them. I made a macro with inline assembly for each of them. The
> problem is that since `endwhere` doesn't have any operands and doesn't
> clobber any registers, the GCC optimization reorders it and places the
> `endwhere` immediately after `where` leaving all the instructions outside
> the block.
That's tricky in general. You want an absolute barrier, but gcc doesn't
really provide one that can be used in inline asm. The closest you can
come is by adding a clobber of "memory":
asm volatile ("xxx" : /* outputs */ : /* inputs */ : "memory");
That will block all instructions that load or store from memory from
moving across the barrier. However, it does not currently block
register changes from moving across the barrier. I don't know whether
that matters to you.
You didn't really describe what these instructions do, but they sound
like looping instructions which ideally gcc would generate itself. They
have some similarity to the existing doloop pattern, q.v. If you can
get gcc to generate the instructions itself, then it seems to me that
you will get better code in general and you won't have to worry about
this issue.
Ian
